`timescale 1ns / 1ps // ------------------------------------------------------------------------------------------------------ // Company: The Learning Labs // Engineer: Mark McDermott // // Create Date: 15:30:47 12/12/2006 // Design Name: iMX21 Processor Mezzanine Board // Module Name: top // Project Name: // Target Devices: CPLD on LL6219 // Tool versions: // Description: // // Dependencies: // // Revision 2.0 - Modified by M.G.Morrow, UW-Madison // Additional Comments: Copyright 2006,2007, 2008 -- DO NOT DISTRIBUTE // ------------------------------------------------------------------------------------------------------ module top(eb, cs0_b, cs1_b, cs2_b, cs3_b, cs5_b, oe_b, rw_b, dtack_imx21, clko, reset_out_b, ext_dmareq_b, ext_dmagrant_b, fpga_clk, fpga_clk_n, fpga_mz_dtack, mz_cpld_clko, mz_cpld_byte, mz_cpld_as, mz_cpld_rw, mz_cpld_misc, mz_cpld_misc_14, mz_cpld_reset_out, address_oe_b, address_dir, data_oe_b, data_dir, x_wr_b, x_rd_b, cpld_int, clko_signal, nfio4, nfio5 ); // --------------------------------------------------------- // INPUTS from iMX21 Processor input [3:0] eb; // byte enables input cs0_b; // /CS0: FLASH access input cs1_b; // /CS1: FPGA access input cs2_b; // /CS2: SDRAM access input cs3_b; // /CS3: ENET access input cs5_b; // /CS5: FPGA access input oe_b; // /OE from ARM input rw_b; // R/W from ARM input clko; // clock input from iMX21 - use this one input clko_signal; // signal input pin input reset_out_b; // /RESET from iMX21 input ext_dmagrant_b; // DMA Grant - Not used due to issues with iMX21 input nfio4; // jumper on mezzanine input nfio5; // jumper on mezzanine input mz_cpld_misc_14; // interrupt from FPGA // --------------------------------------------------------- // INPUTS from FPGA or BASEBOARD input fpga_clk; // Clock from Baseboard Clock Generator input fpga_clk_n; // Clock- from Baseboard Clock Generator input fpga_mz_dtack; // DTACK signal from FPGA (ACTIVE HIGH NOW) // --------------------------------------------------------- // OUTPUT from CPLD to FPGA or BASEBOARD output [3:0] mz_cpld_byte; output mz_cpld_as; // Address strobe to FPGA (ACTIVE HIGH NOW) output mz_cpld_rw; // Read-Write to FPGA output mz_cpld_reset_out; // RESET to FPGA output mz_cpld_clko; // CPLD clock to FPGA output [13:0] mz_cpld_misc; // MISC signals to FPGA // --------------------------------------------------------- // OUTPUT from CPLD to ADDR/DATA buffers output reg address_oe_b; output reg address_dir; output reg data_oe_b; output reg data_dir; // --------------------------------------------------------- // OUTPUT from CPLD to iMX21 // --------------------------------------------------------- output reg dtack_imx21; // /DTACK to iMX21 output ext_dmareq_b; // DMA Request to iMX21 - Not used output cpld_int; // interrupt request to ARM // --------------------------------------------------------- // OUTPUT from CPLD to Mezzanine Memory chips // --------------------------------------------------------- output x_wr_b; output x_rd_b; // --------------------------------------------------------- // Continuous assignments assign x_wr_b = rw_b; // critical timing requirements ************* assign x_rd_b = oe_b; // critical timing requirements ************* assign mz_cpld_clko = clko; // buffer the CPLD clock to FPGA assign mz_cpld_reset_out = reset_out_b; // buffer the RESET to FPGA assign mz_cpld_byte[3:0] = eb[3:0]; // buffer Byte Enables to FPGA assign mz_cpld_rw = rw_b; assign cpld_int = mz_cpld_misc_14; // interrupt signal to iMX21 assign ext_dmareq_b = 1'b1; // disable DMA request wire cs1_rs_b, cs1_ws_b, cs5_rs_b, cs5_ws_b; // read/write strobes to FPGA (active-low) wire arm926_strobe; wire snoop_b = nfio4; // bus snoop control // -------------------------------------------------------------------------------------------- // MISC signal output assignments // -------------------------------------------------------------------------------------------- assign mz_cpld_misc[ 0] = cs1_rs_b; assign mz_cpld_misc[ 1] = cs1_ws_b; assign mz_cpld_misc[ 2] = cs5_rs_b; assign mz_cpld_misc[ 3] = cs5_ws_b; assign mz_cpld_misc[ 4] = oe_b; assign mz_cpld_misc[ 5] = cs0_b; assign mz_cpld_misc[ 6] = cs1_b; assign mz_cpld_misc[ 7] = cs2_b; assign mz_cpld_misc[ 8] = cs3_b; assign mz_cpld_misc[ 9] = cs5_b; assign mz_cpld_misc[10] = nfio4; assign mz_cpld_misc[11] = nfio5; assign mz_cpld_misc[12] = data_dir; assign mz_cpld_misc[13] = data_oe_b; // ------------------------------------------------------------------------------------------------------ // synchronize DTACK from FPGA through 1 flip-flop // ------------------------------------------------------------------------------------------------------ always @(posedge clko or negedge reset_out_b) begin if (!reset_out_b) begin dtack_imx21 <= 1'b1; // negate /DTACK on reset end else begin dtack_imx21 <= fpga_mz_dtack; // synchronize the FPGA /DTACK end end // ------------------------------------------------------------------------------------------------------ // FPGA strobe generation // ------------------------------------------------------------------------------------------------------ assign mz_cpld_as = (~cs1_b | ~cs5_b); // /CS1 or /CS5 active assign cs1_rs_b = ~(~cs1_b & ~oe_b); // read in /CS1 space assign cs1_ws_b = ~(~cs1_b & ~(&eb) & ~rw_b); // write in /CS1 space assign cs5_rs_b = ~(~cs5_b & ~oe_b); // read in /CS5 space assign cs5_ws_b = ~(~cs5_b & ~(&eb) & ~rw_b); // write in /CS1 space assign arm926_strobe = ~cs1_rs_b | ~cs1_ws_b | ~cs5_rs_b | ~cs5_ws_b; // ------------------------------------------------------------------------------------------------------ // TLL6219 transceiver control // ------------------------------------------------------------------------------------------------------ always @ ( * ) begin if(~reset_out_b) begin address_oe_b = 1'b1; // 1 = High-Z during reset only address_dir = 1'b0; // 0 = MZ -> FPGA data_oe_b = 1'b1; // 1 = High-Z during reset only data_dir = 1'b0; // 0 = MZ -> FPGA end else begin address_oe_b = 1'b0; // enable address buffers address_dir = 1'b0; // 0 = MZ -> FPGA if(arm926_strobe) begin // transceivers active during bus cycle strobe period data_oe_b = 1'b0; // enable data buffers data_dir = rw_b; // set to ARM926 bus direction end else if(mz_cpld_as) begin // transceivers disabled during rest of bus cycle data_oe_b = 1'b1; // disable data buffers data_dir = 1'b0; // 0 = MZ -> FPGA end else begin // else enable for snooping (if selected) data_oe_b = snoop_b; // enable controlled by jumper data_dir = 1'b0; // 0 = MZ -> FPGA end end end endmodule