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////////////////////////////////////////////////////////////////////////////
//
// AXI4-Stream interface example
// 
// The purpose of this design is to provide a simple AXI4-Stream interface.
//
// The AXI4-Stream protocol is used as a standard interface to connect components that wish to
// exchange data. The interface can be used to connect a single master, that generates data, to a
// single slave, that receives data. 
// 
////////////////////////////////////////////////////////////////////////////////

//----------------------------------------
// Module Section
//----------------------------------------
`timescale 1ps/1ps

module axi_stream_slave #(
  ////////////////////////////////////////////////////////////////////////////
  // Width of S_AXIS data bus. The slave accepts the read and write data 
  // of width C_S_AXIS_TDATA_WIDTH.
  parameter integer C_S_AXIS_TDATA_NUM_BYTES = 4
) (
  ////////////////////////////////////////////////////////////////////////////
  // Global ports
  input wire AXIS_ACLK,
  input wire AXIS_ARESETN,
  ////////////////////////////////////////////////////////////////////////////
  // Slave Stream Ports
  // TREADY indicates that the slave can accept a transfer in the
  // current cycle.
  output wire S_AXIS_TREADY,
  ////////////////////////////////////////////////////////////////////////////
  // TDATA is the primary payload that is used to provide the data
  // that is passing across the interface to the slave
  input wire [(C_S_AXIS_TDATA_NUM_BYTES*8)-1:0] S_AXIS_TDATA,
  ////////////////////////////////////////////////////////////////////////////
  // TSTRB is the byte qualifier that indicates whether the content
  // of the associated byte of TDATA is processed as a data byte or
  // a position byte.
  input wire [C_S_AXIS_TDATA_NUM_BYTES-1:0] S_AXIS_TSTRB,
  ////////////////////////////////////////////////////////////////////////////
  // TLAST indicates the boundary of a packet.
  input wire S_AXIS_TLAST,
  ////////////////////////////////////////////////////////////////////////////
  // TVALID indicates that the slave is accepting a valid transfer.
  // A transfer takes place when both TVALID and TREADY are asserted.
  input wire S_AXIS_TVALID
);

localparam [1:0]  IDLE      = 2'b00,
                  RCV       = 2'b01,
                  BACKOFF   = 2'b10;

reg [7:0] lsfr_backoff;
wire      lsfr_feedback;
assign lsfr_feedback = !(lsfr_backoff[7] ^ lsfr_backoff[3]);
reg [7:0] intra_packet_backoff;
reg [1:0] state;
reg       axis_tready;

always@(posedge AXIS_ACLK) begin
  if(!AXIS_ARESETN) begin
    lsfr_backoff <= 8'h00;
    state <= IDLE;
    axis_tready <= 1'b0;
  end else begin
    lsfr_backoff <= {lsfr_backoff[6:0], lsfr_feedback};
    case(state)
      IDLE: begin
        intra_packet_backoff <= lsfr_backoff;
        state <= BACKOFF;
        axis_tready <= 1'b0;
      end
      BACKOFF : begin
        intra_packet_backoff <= intra_packet_backoff + 1;
        if (intra_packet_backoff[4:0] == 5'h1f) begin
          state <= RCV;
        end else begin
          state <= BACKOFF;
        end
      end
      RCV: begin
        if (S_AXIS_TVALID && S_AXIS_TREADY && S_AXIS_TLAST) begin
          state <= IDLE;
          axis_tready <= 1'b0;
        end else begin
          axis_tready <= lsfr_backoff[7];
          state <= RCV;
        end
      end
      default : begin
        lsfr_backoff <= 8'h00;
        state <= IDLE;
        axis_tready <= 1'b0;
      end
    endcase
  end
end

assign S_AXIS_TREADY = axis_tready;

endmodule