YourCompanyName.com user axi_master 1.0 M_AXI AWADDR M_AXI_AWADDR AWLEN M_AXI_AWLEN AWSIZE M_AXI_AWSIZE AWBURST M_AXI_AWBURST AWCACHE M_AXI_AWCACHE AWVALID M_AXI_AWVALID AWREADY M_AXI_AWREADY WDATA M_AXI_WDATA WSTRB M_AXI_WSTRB WLAST M_AXI_WLAST WVALID M_AXI_WVALID WREADY M_AXI_WREADY BRESP M_AXI_BRESP BVALID M_AXI_BVALID BREADY M_AXI_BREADY ARADDR M_AXI_ARADDR ARLEN M_AXI_ARLEN ARSIZE M_AXI_ARSIZE ARBURST M_AXI_ARBURST ARCACHE M_AXI_ARCACHE ARVALID M_AXI_ARVALID ARREADY M_AXI_ARREADY RDATA M_AXI_RDATA RRESP M_AXI_RRESP RLAST M_AXI_RLAST RVALID M_AXI_RVALID RREADY M_AXI_RREADY M_AXI_signal_reset RST M_AXI_ARESETN POLARITY ACTIVE_LOW M_AXI_signal_clock CLK M_AXI_ACLK ASSOCIATED_BUSIF M_AXI ASSOCIATED_RESET M_AXI_ARESETN M_AXI 1099511627776 31 xilinx_verilogsynthesis Verilog Synthesis verilogSource:vivado.xilinx.com:synthesis verilog axi_master xilinx_verilogsynthesis_view_fileset xilinx_verilogbehavioralsimulation Verilog Simulation verilogSource:vivado.xilinx.com:simulation verilog axi_master xilinx_verilogbehavioralsimulation_view_fileset xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset WCOMPLETE out wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation RCOMPLETE out wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation M_AXI_ACLK in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation M_AXI_ARESETN in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation M_AXI_AWADDR out 39 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation M_AXI_AWLEN out 7 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation M_AXI_AWSIZE out 2 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation M_AXI_AWBURST out 1 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation M_AXI_AWCACHE out 3 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation M_AXI_AWVALID out wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation M_AXI_AWREADY in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation M_AXI_WDATA out 31 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation M_AXI_WSTRB out 3 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation M_AXI_WLAST out wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation M_AXI_WVALID out wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation M_AXI_WREADY in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation M_AXI_BRESP in 1 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation M_AXI_BVALID in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation M_AXI_BREADY out wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation M_AXI_ARADDR out 39 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation M_AXI_ARLEN out 7 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation M_AXI_ARSIZE out 2 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation M_AXI_ARBURST out 1 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation M_AXI_ARCACHE out 3 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation M_AXI_ARVALID out wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation M_AXI_ARREADY in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation M_AXI_RDATA in 31 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation M_AXI_RRESP in 1 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation M_AXI_RLAST in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation M_AXI_RVALID in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation M_AXI_RREADY out wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation C_TRANSACTIONS_NUM C Transactions Num 10 C_BURST_LEN C Burst Len 16 C_M_AXI_DATA_WIDTH Data Width 32 choices_0 ACTIVE_HIGH ACTIVE_LOW choices_1 32 64 xilinx_verilogsynthesis_view_fileset verilog/axi_master.v verilogSource work xilinx_verilogbehavioralsimulation_view_fileset verilog/axi_master.v verilogSource work xilinx_xpgui_view_fileset xgui/axi_master_v1_0.tcl tclSource axi_master_v1_0 C_M_AXI_DATA_WIDTH Data Width 32 C_BURST_LEN Burst Length Burst Length 16 C_TRANSACTIONS_NUM Number of Transactions Number of Transactions 10 Component_Name axi_master_v1_0 kintex7 virtex7 /Embedded_Processing/AXI_Infrastructure axi_master_v1_0 Your Company Name http://www.YourCompanyName.com 2013-05-29T17:01:17 2013.1