YourCompanyName.com user axi_slave 1.0 S_AXI AWID S_AXI_AWID AWADDR S_AXI_AWADDR AWLEN S_AXI_AWLEN AWSIZE S_AXI_AWSIZE AWBURST S_AXI_AWBURST AWVALID S_AXI_AWVALID AWREADY S_AXI_AWREADY WDATA S_AXI_WDATA WSTRB S_AXI_WSTRB WLAST S_AXI_WLAST WVALID S_AXI_WVALID WREADY S_AXI_WREADY BID S_AXI_BID BRESP S_AXI_BRESP BVALID S_AXI_BVALID BREADY S_AXI_BREADY ARID S_AXI_ARID ARADDR S_AXI_ARADDR ARLEN S_AXI_ARLEN ARSIZE S_AXI_ARSIZE ARBURST S_AXI_ARBURST ARVALID S_AXI_ARVALID ARREADY S_AXI_ARREADY RID S_AXI_RID RDATA S_AXI_RDATA RRESP S_AXI_RRESP RLAST S_AXI_RLAST RVALID S_AXI_RVALID RREADY S_AXI_RREADY S_AXI_signal_reset RST S_AXI_ARESETN POLARITY ACTIVE_LOW S_AXI_signal_clock CLK S_AXI_ACLK ASSOCIATED_BUSIF S_AXI ASSOCIATED_RESET S_AXI_ARESETN S_AXI reg0 0 16384 31 register xilinx_verilogsynthesis Verilog Synthesis verilogSource:vivado.xilinx.com:synthesis verilog axi_slave xilinx_verilogsynthesis_view_fileset xilinx_verilogbehavioralsimulation Verilog Simulation verilogSource:vivado.xilinx.com:simulation verilog axi_slave xilinx_verilogbehavioralsimulation_view_fileset xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset S_AXI_ACLK in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation S_AXI_ARESETN in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation S_AXI_AWID in 0 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation S_AXI_AWADDR in 13 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation S_AXI_AWLEN in 7 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation S_AXI_AWSIZE in 2 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation S_AXI_AWBURST in 1 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation S_AXI_AWVALID in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation S_AXI_AWREADY out wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation S_AXI_WDATA in 31 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation S_AXI_WSTRB in 3 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation S_AXI_WLAST in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation S_AXI_WVALID in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation S_AXI_WREADY out wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation S_AXI_BID out 0 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation S_AXI_BRESP out 1 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation S_AXI_BVALID out wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation S_AXI_BREADY in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation S_AXI_ARID in 0 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation S_AXI_ARADDR in 13 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation S_AXI_ARLEN in 7 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation S_AXI_ARSIZE in 2 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation S_AXI_ARBURST in 1 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation S_AXI_ARVALID in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation S_AXI_ARREADY out wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation S_AXI_RID out 0 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation S_AXI_RDATA out 31 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation S_AXI_RRESP out 1 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation S_AXI_RLAST out wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation S_AXI_RVALID out wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation S_AXI_RREADY in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation C_S_AXI_ID_WIDTH C S Axi Id Width 1 C_S_AXI_DATA_WIDTH Data Width 32 choices_0 ACTIVE_HIGH ACTIVE_LOW choices_1 32 64 xilinx_verilogsynthesis_view_fileset verilog/axi_slave.v verilogSource work xilinx_verilogbehavioralsimulation_view_fileset verilog/axi_slave.v verilogSource work xilinx_xpgui_view_fileset xgui/axi_slave_v1_0.tcl tclSource axi_slave_v1_0 C_S_AXI_DATA_WIDTH Data Width 32 C_S_AXI_ID_WIDTH ID Width ID Width 1 Component_Name axi_slave_v1_0 kintex7 virtex7 /Embedded_Processing/AXI_Infrastructure axi_slave_v1_0 Your Company Name http://www.YourCompanyName.com 2013-05-29T17:01:14 2013.1