./scripts
|   --  common
|   --  dc
|   --  formality
|   --  fulltree.sh
|   --  icc
|   --  mc
|   --  primetime
|   --  ptpx
|   --  readme
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| common:
|   --  common.tcl         : NOT modified.
|   --  constraints.sdc    : The appropriate clock periods and false paths have been updated. 
|   --  rtl.list           : NOT modified.
|   --  synopsys.procs.tcl : NOT modified.
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| dc:
|   --  dc.tcl             : In the first run, set the variable 'DO_TOPO' as false.
                             After one dummy run of the script ../icc/icc.tcl, set the variable to true and run all over again.
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| formality:
|   --  fm_post_eco.tcl    : DC netlist vs ICC netlist after ECO fixed have been done.
|   --  fm.tcl             : RTL vs DC netlist.
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| icc:
|   --  floorplan.tcl      : Floorplan description file.
|   --  icc_eco.tcl        : Once, the 1st round of ICC run is completed after running the script icc.tcl, run the 1st iteration of pt_eco.tcl script at SS corner
                             Now, run the first round of ICC ECO by setting the variable 'iteration' to 'one', the results are dumped in results_iter${iteration}
                             Again run the PT ECO at the same corner followed by ICC ECO run with 'iteration' set to 'two'. We expect all the setup and hold
                             violations to be fixed at SS corner.
                             Now, again run PT ECO iteration three at FF corner, followed by ICC ECO run with 'iteration' set to 'three' and without changing the
                             'corner' variable. Finally, run PT ECO 4th iteration at the FF corner again fololowed by ICC ECO with 'iteration' set to 'four'.
                             By now, all the setup and hold violations should be fixed cross corner. This could be checked by running the script pt_final.tcl
                             in the primetime folder by checking at all corners.
|   --  icc.tcl            : Inital ICC run script after DC has been run in topo mode.
|   --  pad_plan.tcl       : Location of Virtual VDD and VSS pads.
|   --  pin_constraint.tcl : Location of the rest of the pins in the design.
|   --  powergrid.tcl      : Power grid specification of the design
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| mc: Ignore the contents of this folder as the memory compiler is not functional.
|   --  demo
|   --  setup.sh
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	| demo:
	|   --  SRAM4x16_90nm.config
	|   --  SRAM4x16.config
	|   --  SRAM4x16_duallp.config
	|   --  SRAM8x32_single90nm.config
	|   --  SRAM8x32_single.config
	|   --  SRAM8x32_singlelp.config
	-------------------------------------------------------------------------------------
| primetime:
|   --  pt_eco.tcl  : Run the respective 'iteration' for the succeeding ICC ECO run.
                      For first two iterations set the variable 'corner' as ss0p95vn40c and for the next two as ff1p16v125c.
                      The results of the run i.e. eco_icc.tcl will be dumped under the folder results_iter${iteration}.
|   --  pt_final.tcl: We expect the ECO fixes to be done in 4 iterations and the results will be dumped in icc/results_iter4
                      Run this script to dump the timing reports cross corner by setting the variable 'corner' as ff1p16v125c, tt1p05v25c and ss0p95vn40c
|   --  pt.tcl      : Optional script. This only dumps the timing reports for first ICC run.
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| ptpx:
|   --  ptpx_activity.tcl : Activity file with appropriate clock periods.
|   --  ptpx_post_eco.tcl : After four iterations of ECO fixes, the final ICC results are dumped under icc/results_iter4.
                            Once, ECO fixes are done, run this script to dump the final power reports
|   --  ptpx.tcl          : Run this script after the first successful ICC run to dump the power reports of the design before ECO fixes.
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