`ifdef VCS
`else
`delay_mode_path
`endif
`timescale 1 ns / 10 ps

`celldefine

module AND2_H (Z,A,B);

  output  Z;
  input  A;
  input  B;

  AND2  i0 (Z,A,B);

specify

  (A +=> Z) = (0.0:0.0:0.0, 0.0:0.0:0.0);
  (B +=> Z) = (0.0:0.0:0.0, 0.0:0.0:0.0);
endspecify

endmodule
`endcelldefine