`ifdef VCS
`else
`delay_mode_path
`endif
`timescale 1 ns / 10 ps

`celldefine

module AO22_I (Z,A1,A2,B1,B2);

  output  Z;
  input  A1;
  input  A2;
  input  B1;
  input  B2;

  AO22  i0 (Z,A1,A2,B1,B2);

specify

  (A1 +=> Z) = (0.0:0.0:0.0, 0.0:0.0:0.0);
  (A2 +=> Z) = (0.0:0.0:0.0, 0.0:0.0:0.0);
  (B1 +=> Z) = (0.0:0.0:0.0, 0.0:0.0:0.0);
  (B2 +=> Z) = (0.0:0.0:0.0, 0.0:0.0:0.0);
endspecify

endmodule
`endcelldefine