module BD (PAD, PT);
inout PAD, PT;

reg c1, c2;

initial begin
 c1=1'b0;
 c2=1'b0;
end

nmos  A1  (PAD, n, c1);
nmos  A3  (n, PT, 1);

nmos  A2  (PT, m, c2);
nmos  A4  (m, PAD, 1);

always @(m)
 if (m !== n) begin
   c1 = 0;
   c2 = 1;
 end

always @(n)
 if (m !== n) begin
   c1 = 1;
   c2 = 0;
 end

endmodule