`ifdef VCS
`else
`delay_mode_path
`endif
`timescale 1 ns / 10 ps

`celldefine

module COMP2_D (Z,A1,A2,B1,B2);

  output  Z;
  input  A1;
  input  A2;
  input  B1;
  input  B2;

  COMP2  i0 (Z,A1,A2,B1,B2);

specify

if(A1)
  (posedge A1 => (Z:A1) ) = (0.0:0.0:0.0, 0.0:0.0:0.0);
if(!A1)
  (negedge A1 => (Z:A1) ) = (0.0:0.0:0.0, 0.0:0.0:0.0);
if(A2)
  (posedge A2 => (Z:A2) ) = (0.0:0.0:0.0, 0.0:0.0:0.0);
if(!A2)
  (negedge A2 => (Z:A2) ) = (0.0:0.0:0.0, 0.0:0.0:0.0);
if(B1)
  (posedge B1 => (Z:B1) ) = (0.0:0.0:0.0, 0.0:0.0:0.0);
if(!B1)
  (negedge B1 => (Z:B1) ) = (0.0:0.0:0.0, 0.0:0.0:0.0);
if(B2)
  (posedge B2 => (Z:B2) ) = (0.0:0.0:0.0, 0.0:0.0:0.0);
if(!B2)
  (negedge B2 => (Z:B2) ) = (0.0:0.0:0.0, 0.0:0.0:0.0);
endspecify

endmodule
`endcelldefine