`ifdef VCS
`else
`delay_mode_path
`endif
`timescale 1 ns / 10 ps

`celldefine

module DELAY6_C (Z,A);

  output  Z;
  input  A;

  DELAY6  i0 (Z,A);

specify


  `ifdef DELAY_CELL_NOM_DLY
    specparam tech_dly = 0.555;
  `else
  `ifdef DELAY_CELL_ZERO_DLY
    specparam tech_dly = 0.0;
  `else
    specparam tech_dly = 0.2;
  `endif
  `endif

  (A +=> Z) = (tech_dly:tech_dly:tech_dly , tech_dly:tech_dly:tech_dly);
endspecify

endmodule
`endcelldefine