module DFFSR_CBS (L2,D,E,S,R);
input D,E,S,R;
output L2;

reg L2;

always @(posedge E)
  if (S && R)
    L2 <= D;
  else
    casez({S,R,D})
      3'b01? : L2 <= 1;
      3'b10? : L2 <= 0;
      3'bx11 : L2 <= 1;
      3'b1x0 : L2 <= 0;
      default: L2 <= 1'bx;
    endcase

always @(E or S or R)
  if(E)
    if (S && R) ;
    else
      casez ({S,R,L2})
        3'b01? : L2 = 1;
        3'b10? : L2 = 0;
        3'bx11 : L2 = 1;
        3'b1x0 : L2 = 0;
        default: L2 = 1'bx;
      endcase

endmodule