module DFFSR_L2N_CBS (L2,L2N,D,E,S,R);
input D,E,S,R;
output L2,L2N;

reg L2;
reg L2N;

always @(posedge E)
    begin
      L2 <= D;
      L2N <= !D;
    end
    begin
      L2  <= 0;
      L2N <= 0;
    end
  else
    begin
      casez({S,R,D})
        3'b01? : L2 <= 1;
        3'b10? : L2 <= 0;
        3'bx11 : L2 <= 1;
        3'b1x0 : L2 <= 0;
        default: L2 <= 1'bx;
      endcase
      L2N = !L2;
    end

  if (S && R) ;
    begin
      L2  = 0;
      L2N = 0;
    end
  else
    begin
      casez ({S,R,L2})
        3'b01? : L2 = 1;
        3'b10? : L2 = 0;
        3'bx11 : L2 = 1;
        3'b1x0 : L2 = 0;
        default: L2 = 1'bx;
      endcase
      L2N = !L2;
    end
endmodule