`ifdef VCS
`else
`delay_mode_path
`endif
`timescale 1 ns / 10 ps

`celldefine

module DFF_K (Q,QBAR,CLK,D);

  output  Q;
  output  QBAR;
  input  CLK;
  input  D;

  reg    notifier;
  DFF  i0 (Q,QBAR,CLK,D,notifier);

specify

  (posedge CLK => (Q +: CLK)) = (0.1:0.1:0.1, 0.1:0.1:0.1);
  (posedge CLK => (QBAR +: CLK)) = (0.1:0.1:0.1, 0.1:0.1:0.1);
  $setuphold (posedge CLK,posedge D,0.09,0.09,notifier);
  $setuphold (posedge CLK,negedge D,0.09,0.09,notifier);
  $width (negedge CLK,0.4,0,notifier);
  $width (posedge CLK,0.4,0,notifier);
endspecify

endmodule
`endcelldefine