`timescale 1 ns / 1 ps

module DIV5S6MP (clkDiv, M0, M1, inClk);
   output     clkDiv;
   input      M0;
   input      M1;
   input      inClk;

   reg        inClkPrime;
   real       cycle_time;
   integer    check_one;
   real       delay;
   real       multFactor;

assign clkDiv = ((M0==0) && (M1==0)) ? inClk : inClkPrime;

initial begin
  delay         = 50;
  inClkPrime    = 1'b0;
  #0 inClkPrime = 1'b1;
end


always @ ({M1,M0}) begin

  casez ({M1,M0})
    2'b00: multFactor = 1.0000;
    2'b01: multFactor = 3.2959;
    2'b10: multFactor = 1.1958;
    2'b11: multFactor = 1.0987;
  endcase

  delay = cycle_time * multFactor / 2.0;
end

/* measure cycle time of input clock */
always @ (posedge inClk) begin
   check_one = $time;
   @ (posedge inClk)  cycle_time = $time - check_one ;
end

/* also, sync up the PO0prime signal */
always @ (posedge inClk) begin
   delay = cycle_time * multFactor / 2.0;
end

always @(posedge inClkPrime) begin
  if (delay == 0) begin
    delay = 50;
  end
  #delay inClkPrime = 1'b0;
end

always @(negedge inClkPrime) begin
  #delay inClkPrime = 1'b1;
end
endmodule