`timescale 100 ps / 100 ps

module DLY90 (dlyClk, inClk);
  output dlyClk;
  input  inClk;

  reg    dlyClk;

  integer   check_one;
  integer   dly_time;

initial begin
   dly_time = 0;
end

/* measure delay time based on input clock */
always @ (posedge inClk) begin
   check_one = $time;
   @ (posedge inClk)  dly_time = ($time - check_one) / 4;

`ifdef DEBUG_DLY90
   $display ("DLY90: Cycle time=%d  Delay=%d", ($time - check_one), dly_time);
`endif

end

always @(inClk)
  dlyClk = #(dly_time) inClk;

endmodule