module FREQDIV (clk_2, clk);
   output clk_2;
   input  clk;

   reg     clk_2;

   always @ (clk)
      if ( clk === 1'bx )  clk_2 = 1'bx;
      else if ( clk_2 === 1'bx )  clk_2 = 1;
      else if ( clk == 1'b0 )  @ ( posedge clk )  clk_2 = ~clk_2;

endmodule