module GRAM_SRL_1 (P10,P30,PA0,PB0,PC0,PD0,PI0,INPHASE);
  output  P10;
  output  P30;
  input   PA0;
  input   PB0;
  input   PC0;
  input   PD0;
  input   PI0;
  input   INPHASE;

`ifdef LV
  wire P10_int;

  LV_LSSD2 GR_l1 (.L2(P30), .L1(P10_int), .A(PA0), .B(PB0), .C(PC0), .D(PD0), .I(PI0) );
  LV_MUX   GR_l2 (.A(P10_int),.B(P30),.S(INPHASE),.Y(P10));

`else

  PH2P  l1  (P10,PA0,PC0,PI0,PD0);
  PH1P  l2  (P30,PB0,P10);

`endif
endmodule