`ifdef VCS
`else
`delay_mode_path
`endif
`timescale 1 ns / 10 ps

`celldefine

module INVERT_J (Z,A);

  output  Z;
  input  A;

  INVERT  i0 (Z,A);

specify

  (A -=> Z) = (0.0:0.0:0.0, 0.0:0.0:0.0);
endspecify

endmodule
`endcelldefine