`celldefine
module LPRABYP_P2 (RBL0P1, RBL1P1, SO1, SO2, AT, BT, MS, SI1, SI2, RWL0P1,
                   RWL1P1, WBLP1, WBS0P1T, WBS1P1T, WWL0P1T, WWL1P1T);
   input  AT;
   input  BT;
   input  MS;
   input  RWL0P1;
   input  RWL1P1;
   input  WWL0P1T;
   input  WWL1P1T;
   input  WBS0P1T;
   input  WBS1P1T;
   input  WBLP1;
   input  SI1;
   input  SI2;
   output SO1;
   output SO2;
   output RBL0P1;
   output RBL1P1;

   wire net00;
   wire net01;
   wire net02;
   wire net03;
   wire net04;
   wire net06;

   and  I0(net00, WWL0P1T, WBS0P1T);
   and  I1(net01, WWL1P1T, WBS0P1T);
   and  I2(net02, WWL0P1T, WBS1P1T);
   and  I3(net03, WWL1P1T, WBS1P1T);

`ifdef LV

  RA_FF_2 W2 (.SD1(net02), .SD2(net01), .DATA1(SI1), .P01DCLK(AT),    .MDATA(WBLP1),
              .BCLK(BT),   .L2OUT(SO1), .MS(MS),     .MUXOUT1(net04), .MUXOUT2(net05) );
  RA_FF_2 W0 (.SD1(net03), .SD2(net00), .DATA1(SI2), .P01DCLK(AT),    .MDATA(WBLP1),
              .BCLK(BT),   .L2OUT(SO2), .MS(MS),     .MUXOUT1(net06), .MUXOUT2(netSO) );


    bufif1 bus1 (RBL1P1,net06,RWL1P1);
    bufif1 bus2 (RBL1P1,net04,RWL0P1);
    bufif1 bus3 (RBL0P1,net05,RWL1P1);
    bufif1 bus4 (RBL0P1,netSO,RWL0P1);

   pulldown (pull0,pull1) (RBL1P1);
   pulldown (pull0,pull1) (RBL0P1);

`else

     PH2P_2 W2 (.L1OUT(net04),.L2OUT(SO1),
                .CLK1(AT),.CLK2(net02),.CLK3(BT),.CLK4(net01),
                .DATA1(SI1),.DATA2(WBLP1),.DATA3(net04),.DATA4(WBLP1));
     PH2P_2 W0 (.L1OUT(net06),.L2OUT(SO2),
                .CLK1(AT),.CLK2(net03),.CLK3(BT),.CLK4(net00),
                .DATA1(SI2),.DATA2(WBLP1),.DATA3(net06),.DATA4(WBLP1));

 bufif1 I4 (RBL1P1, net06, RWL1P1);
 bufif1 I5 (RBL1P1, net04, RWL0P1);
 bufif1 I6 (RBL0P1, SO1  , RWL1P1);
 bufif1 I7 (RBL0P1, SO2  , RWL0P1);

`endif

endmodule
`endcelldefine