module LPRABYP_P4 (RBL0P1, RBL0P2, RBL1P1, RBL1P2, SO1, SO2, AT, BT, MS,
                   SI1, SI2, RWL0P1, RWL0P2, RWL1P1, RWL1P2, WBLP1, WBLP2,
                   WBS0P1T, WBS0P2T, WBS1P1T, WBS1P2T, WWL0P1T, WWL0P2T,
                   WWL1P1T, WWL1P2T);
   input  AT;
   input  BT;
   input  MS;
   input  RWL0P1;
   input  RWL1P1;
   input  RWL0P2;
   input  RWL1P2;
   input  WWL0P1T;
   input  WWL1P1T;
   input  WWL0P2T;
   input  WWL1P2T;
   input  WBS0P1T;
   input  WBS1P1T;
   input  WBS0P2T;
   input  WBS1P2T;
   input  WBLP1;
   input  WBLP2;
   input  SI1;
   input  SI2;
   output SO1;
   output SO2;
   output RBL0P1;
   output RBL1P1;
   output RBL0P2;
   output RBL1P2;

   wire net00;
   wire net01;
   wire net02;
   wire net03;
   wire net002;
   wire net012;
   wire net022;
   wire net032;
   wire net04;
   wire net06;


   and   I0 (net00, WWL0P1T, WBS0P1T);
   and   I1 (net01, WWL1P1T, WBS0P1T);
   and   I2 (net02, WWL0P1T, WBS1P1T);
   and   I3 (net03, WWL1P1T, WBS1P1T);

   and   I02 (net002, WWL0P2T, WBS0P2T);
   and   I12 (net012, WWL1P2T, WBS0P2T);
   and   I22 (net022, WWL0P2T, WBS1P2T);
   and   I32 (net032, WWL1P2T, WBS1P2T);

`ifdef LV

  RA_FF_3 W2 (.SD1(net02), .SD2(net022), .SD3(net01), .SD4(net012), .DATA1(SI1), .P01DCLK(AT),
              .MDATA1(WBLP1), .MDATA2(WBLP2),
              .BCLK(BT),   .L2OUT(SO1),  .MS(MS),  .MUXOUT1(net04), .MUXOUT3(net05) );
  RA_FF_3 W0 (.SD1(net03), .SD2(net032), .SD3(net00), .SD4(net002), .DATA1(SI2), .P01DCLK(AT),
              .MDATA1(WBLP1), .MDATA2(WBLP2),
              .BCLK(BT),   .L2OUT(SO2),   .MS(MS),  .MUXOUT1(net06), .MUXOUT3(netSO) );


    bufif1 bus1 (RBL1P1, net06, RWL1P1);
    bufif1 bus2 (RBL1P1, net04, RWL0P1);
    bufif1 bus3 (RBL0P1, net05, RWL1P1);
    bufif1 bus4 (RBL0P1, netSO, RWL0P1);

    bufif1 bus5 (RBL1P2, net06, RWL1P2);
    bufif1 bus6 (RBL1P2, net04, RWL0P2);
    bufif1 bus7 (RBL0P2, net05, RWL1P2);
    bufif1 bus8 (RBL0P2, netSO, RWL0P2);


`else
     PH3P_2 W2 (.L1OUT(net04),.L2OUT(SO1),
                .CLK1(AT),.CLK2(net02),.CLK3(net022),
                .CLK4(BT),.CLK5(net01),.CLK6(net012),
                .DATA1(SI1),  .DATA2(WBLP1),.DATA3(WBLP2),
                .DATA4(net04),.DATA5(WBLP1),.DATA6(WBLP2));
     PH3P_2 W0 (.L1OUT(net06),.L2OUT(SO2),
                .CLK1(AT),.CLK2(net03),.CLK3(net032),
                .CLK4(BT),.CLK5(net00),.CLK6(net002),
                .DATA1(SI2),  .DATA2(WBLP1),.DATA3(WBLP2),
                .DATA4(net06),.DATA5(WBLP1),.DATA6(WBLP2));

   bufif1  I4 (RBL1P1,  net06, RWL1P1);
   bufif1  I5 (RBL1P1,  net04, RWL0P1);
   bufif1  I6 (RBL0P1,  SO1  , RWL1P1);
   bufif1  I7 (RBL0P1,  SO2  , RWL0P1);

   bufif1  I42 (RBL1P2, net06, RWL1P2);
   bufif1  I52 (RBL1P2, net04, RWL0P2);
   bufif1  I62 (RBL0P2, SO1  , RWL1P2);
   bufif1  I72 (RBL0P2, SO2  , RWL0P2);

`endif

endmodule