module LPRABYP_P5 (RBL0P1, RBL0P2, RBL0P3, RBL1P1, RBL1P2, RBL1P3,
                   SO1, SO2, AT, BT, MS, SI1, SI2,
                   RWL0P1, RWL0P2, RWL0P3, RWL1P1, RWL1P2, RWL1P3,
                   WBLP1, WBLP2, WBS0P1T, WBS0P2T, WBS1P1T, WBS1P2T,
                   WWL0P1T, WWL0P2T, WWL1P1T, WWL1P2T);
 input    AT;
 input    BT;
 input    MS;
 input    RWL0P1;
 input    RWL1P1;
 input    RWL0P2;
 input    RWL1P2;
 input    RWL0P3;
 input    RWL1P3;
 input    WWL0P1T;
 input    WWL1P1T;
 input    WWL0P2T;
 input    WWL1P2T;
 input    WBS0P1T;
 input    WBS1P1T;
 input    WBS0P2T;
 input    WBS1P2T;
 input    WBLP1;
 input    WBLP2;
 input    SI1;
 input    SI2;
 output   SO1;
 output   SO2;
 output   RBL0P1;
 output   RBL1P1;
 output   RBL0P2;
 output   RBL1P2;
 output   RBL0P3;
 output   RBL1P3;


   and   I0  (net00, WBS0P1T, WWL0P1T);
   and   I1  (net01, WBS0P1T, WWL1P1T);
   and   I2  (net02, WBS1P1T, WWL0P1T);
   and   I3  (net03, WBS1P1T, WWL1P1T);

   and   I02 (net002, WBS0P2T, WWL0P2T);
   and   I12 (net012, WBS0P2T, WWL1P2T);
   and   I22 (net022, WBS1P2T, WWL0P2T);
   and   I32 (net032, WBS1P2T, WWL1P2T);


`ifdef LV

  RA_FF_3 W2 (.SD1(net02), .SD2(net022), .SD3(net01), .SD4(net012), .DATA1(SI1), .P01DCLK(AT),
              .MDATA1(WBLP1), .MDATA2(WBLP2),
              .BCLK(BT),   .L2OUT(SO1),  .MS(MS),  .MUXOUT1(net04), .MUXOUT3(net05) );
  RA_FF_3 W0 (.SD1(net03), .SD2(net032), .SD3(net00), .SD4(net002), .DATA1(SI2), .P01DCLK(AT),
              .MDATA1(WBLP1), .MDATA2(WBLP2),
              .BCLK(BT),   .L2OUT(SO2),   .MS(MS),  .MUXOUT1(net06), .MUXOUT3(netSO) );

    bufif1 bus1 (RBL1P1, net06, RWL1P1);
    bufif1 bus2 (RBL1P1, net04, RWL0P1);
    bufif1 bus3 (RBL0P1, net05, RWL1P1);
    bufif1 bus4 (RBL0P1, netSO, RWL0P1);

    bufif1 bus5 (RBL1P2, net06, RWL1P2);
    bufif1 bus6 (RBL1P2, net04, RWL0P2);
    bufif1 bus7 (RBL0P2, net05, RWL1P2);
    bufif1 bus8 (RBL0P2, netSO, RWL0P2);

    bufif1 bus9  (RBL1P3, net06, RWL1P3);
    bufif1 bus10 (RBL1P3, net04, RWL0P3);
    bufif1 bus11 (RBL0P3, net05, RWL1P3);
    bufif1 bus12 (RBL0P3, netSO, RWL0P3);

`else

   PH3P  W1 (net04, AT, net02, net022, SI1, WBLP1, WBLP2);
   PH3P  W2 (net15, BT, net01, net012, net04, WBLP1, WBLP2);
   PH3P  W3 (net06, AT, net03, net032, SI2, WBLP1, WBLP2);
   PH3P  W0 (net17, BT, net00, net002, net06, WBLP1, WBLP2);

   buf B1 (SO1, net15);
   buf B2 (SO2, net17);

   bufif1  I4 (RBL1P1,  net06, RWL1P1);
   bufif1  I5 (RBL1P1,  net04, RWL0P1);
   bufif1  I6 (RBL0P1,  net15, RWL1P1);
   bufif1  I7 (RBL0P1,  net17, RWL0P1);

   bufif1  I42 (RBL1P2, net06, RWL1P2);
   bufif1  I52 (RBL1P2, net04, RWL0P2);
   bufif1  I62 (RBL0P2, net15, RWL1P2);
   bufif1  I72 (RBL0P2, net17, RWL0P2);

   bufif1  IB4 (RBL1P3,  net06, RWL1P3);
   bufif1  IB5 (RBL1P3,  net04, RWL0P3);
   bufif1  IB6 (RBL0P3,  net15, RWL1P3);
   bufif1  IB7 (RBL0P3,  net17, RWL0P3);

`endif

endmodule