`ifdef VCS
`else
`delay_mode_path
`endif
`timescale 1 ns / 10 ps

`celldefine

module MUX21BAL_H (Z,D0,D1,SD);

  output  Z;
  input  D0;
  input  D1;
  input  SD;

  MUX21BAL  i0 (Z,D0,D1,SD);

specify

  (D0 +=> Z) = (0.0:0.0:0.0, 0.0:0.0:0.0);
  (D1 +=> Z) = (0.0:0.0:0.0, 0.0:0.0:0.0);
if(SD)
  (posedge SD => (Z:SD) ) = (0.0:0.0:0.0, 0.0:0.0:0.0);
if(!SD)
  (negedge SD => (Z:SD) ) = (0.0:0.0:0.0, 0.0:0.0:0.0);
endspecify

endmodule
`endcelldefine