`ifdef VCS
`else
`delay_mode_path
`endif
`timescale 1 ns / 10 ps

`celldefine

module MUX41_J (Z,D0,D1,D2,D3,SD1,SD2);

  output  Z;
  input  D0;
  input  D1;
  input  D2;
  input  D3;
  input  SD1;
  input  SD2;

  MUX41  i0 (Z,D0,D1,D2,D3,SD1,SD2);

specify

  (D0 +=> Z) = (0.0:0.0:0.0, 0.0:0.0:0.0);
  (D1 +=> Z) = (0.0:0.0:0.0, 0.0:0.0:0.0);
  (D2 +=> Z) = (0.0:0.0:0.0, 0.0:0.0:0.0);
  (D3 +=> Z) = (0.0:0.0:0.0, 0.0:0.0:0.0);
if(SD1)
  (posedge SD1 => (Z:SD1) ) = (0.0:0.0:0.0, 0.0:0.0:0.0);
if(!SD1)
  (negedge SD1 => (Z:SD1) ) = (0.0:0.0:0.0, 0.0:0.0:0.0);
if(SD2)
  (posedge SD2 => (Z:SD2) ) = (0.0:0.0:0.0, 0.0:0.0:0.0);
if(!SD2)
  (negedge SD2 => (Z:SD2) ) = (0.0:0.0:0.0, 0.0:0.0:0.0);
endspecify

endmodule
`endcelldefine