module  MUXDLATCH (L2,A,B,C,D,I,SD);

  output  L2;
  input   A;
  input   B;
  input   C;
  input   D;
  input   I;
  input   SD;

  wire net1, net2, net3, P10, P30;


  not i1 (net3, SD);
  and a1 (net1, net3, D);
  or  o1 (net2, net1, P30);
  buf b1 (L2, P30);


`ifdef LV

  LV_LSSD2 lv_latch (.L2(P30), .L1(P10), .A(A), .B(B), .C(C), .D(net2), .I(I) );

`else

  PH2P  l1  (P10,A,C,I,net2);
  PH1P  l2  (P30,B,P10);

`endif

endmodule