module  MUXDLATCH2 (L2,A,B,C,D0,D1,I,SD);

  output  L2;
  input   A;
  input   B;
  input   C;
  input   D0, D1;
  input   I;
  input   SD;

  wire net1, net2, NSD;

not not1 ( NSD, SD );
and and1 ( net1, D0, NSD );
and and2 ( net2, D1, SD );
or or1 ( MUX20_OUT, net1, net2 );

`ifdef LV
  LV_LSSD2 lv_latch (.L2(L2), .L1(l1out), .A(A), .B(B), .C(C), .D(MUX20_OUT), .I(I) );
`else
  PH2P l1 ( l1out, A, C, I, MUX20_OUT );
  PH1P l2 ( L2, B, l1out );
`endif

endmodule