module PH5PRD (LOUT, CLK1, CLK2, CLK3, CLK4, CLK5, DATA1, DATA2, DATA3, DATA4, DATA5, RESET);
    input CLK1;
    input CLK2;
    input CLK3;
    input CLK4;
    input CLK5;
    input DATA1;
    input DATA2;
    input DATA3;
    input DATA4;
    input DATA5;
    input RESET;

    wire loutpc1, loutpc2, loutpc3, orclks1, orclks2, orclks3;

    PH2PC  pc1 (loutpc1, CLK2, CLK3, DATA2, DATA3, LOUT);
    or     o1  (orclks1, CLK2, CLK3);

    PH2PC  pc2 (loutpc2, CLK4, CLK5, DATA4, DATA5, LOUT);
    or     o2  (orclks2, CLK4, CLK5);

    PH2PC  pc3 (loutpc3, orclks1, orclks2, loutpc1, loutpc2, LOUT);
    or     o3  (orclks3, orclks1, orclks2);

    PH2PRD p1  (LOUT, CLK1, orclks3, DATA1, loutpc3, RESET);

endmodule