`ifdef VCS
`else
`delay_mode_path
`endif
`timescale 1 ns / 10 ps

`celldefine

module SLATSR_E (Q,QBAR,CLK,D,RN,S,SE,SI);

  output  Q;
  output  QBAR;
  input  CLK;
  input  D;
  input  RN;
  input  S;
  input  SE;
  input  SI;

  reg    notifier;
  SLATSR  i0 (Q,QBAR,CLK,D,RN,S,SE,SI,notifier);

`ifdef LV
`else
  not n1 (nS,S);
  and g1 (nS_and_RN,nS,RN);
  
`endif

specify

  (posedge CLK => (Q +: CLK)) = (0.1:0.1:0.1, 0.1:0.1:0.1);
  (D +=> Q) = (0.0:0.0:0.0, 0.0:0.0:0.0);
  (negedge RN => (Q +: RN)) = (0.1:0.1:0.1, 0.1:0.1:0.1);
  (posedge S => (Q +: S)) = (0.1:0.1:0.1, 0.1:0.1:0.1);
  (SI +=> Q) = (0.0:0.0:0.0, 0.0:0.0:0.0);
  (posedge CLK => (QBAR +: CLK)) = (0.1:0.1:0.1, 0.1:0.1:0.1);
  (D -=> QBAR) = (0.0:0.0:0.0, 0.0:0.0:0.0);
  (negedge RN => (QBAR -: RN)) = (0.1:0.1:0.1, 0.1:0.1:0.1);
  (posedge S => (QBAR -: S)) = (0.1:0.1:0.1, 0.1:0.1:0.1);
  (SI -=> QBAR) = (0.0:0.0:0.0, 0.0:0.0:0.0);
  $setuphold (negedge CLK &&& nS_and_RN,posedge D,0.09,0.09,notifier);
  $setuphold (negedge CLK &&& nS_and_RN,negedge D,0.09,0.09,notifier);
  $setuphold (negedge CLK,posedge RN,0.09,0.09,notifier);
  $setuphold (negedge CLK,negedge S,0.09,0.09,notifier);
  $setuphold (negedge CLK,posedge SE,0.09,0.09,notifier);
  $setuphold (negedge CLK,negedge SE,0.09,0.09,notifier);
  $setuphold (negedge CLK &&& nS_and_RN,posedge SI,0.09,0.09,notifier);
  $setuphold (negedge CLK &&& nS_and_RN,negedge SI,0.09,0.09,notifier);
  $width (posedge CLK &&& nS_and_RN,0.4,0,notifier);
  $width (negedge RN,0.4,0,notifier);
  $width (posedge S,0.4,0,notifier);
endspecify

endmodule
`endcelldefine