`ifdef VCS
`else
`delay_mode_path
`endif
`timescale 1 ns / 10 ps

`celldefine

module XNOR3_B (Z,A,B,C);

  output  Z;
  input  A;
  input  B;
  input  C;

  XNOR3  i0 (Z,A,B,C);

specify

if(A)
  (posedge A => (Z:A) ) = (0.0:0.0:0.0, 0.0:0.0:0.0);
if(!A)
  (negedge A => (Z:A) ) = (0.0:0.0:0.0, 0.0:0.0:0.0);
if(B)
  (posedge B => (Z:B) ) = (0.0:0.0:0.0, 0.0:0.0:0.0);
if(!B)
  (negedge B => (Z:B) ) = (0.0:0.0:0.0, 0.0:0.0:0.0);
if(C)
  (posedge C => (Z:C) ) = (0.0:0.0:0.0, 0.0:0.0:0.0);
if(!C)
  (negedge C => (Z:C) ) = (0.0:0.0:0.0, 0.0:0.0:0.0);
endspecify

endmodule
`endcelldefine