`ifdef VCS
`else
`delay_mode_path
`endif
`timescale 1 ns / 10 ps

`celldefine

module XOR9_H (Z,A,B,C,D,E,F,G,H,I);

  output  Z;
  input  A;
  input  B;
  input  C;
  input  D;
  input  E;
  input  F;
  input  G;
  input  H;
  input  I;

  XOR9  i0 (Z,A,B,C,D,E,F,G,H,I);

specify

if(A)
  (posedge A => (Z:A) ) = (0.0:0.0:0.0, 0.0:0.0:0.0);
if(!A)
  (negedge A => (Z:A) ) = (0.0:0.0:0.0, 0.0:0.0:0.0);
if(B)
  (posedge B => (Z:B) ) = (0.0:0.0:0.0, 0.0:0.0:0.0);
if(!B)
  (negedge B => (Z:B) ) = (0.0:0.0:0.0, 0.0:0.0:0.0);
if(C)
  (posedge C => (Z:C) ) = (0.0:0.0:0.0, 0.0:0.0:0.0);
if(!C)
  (negedge C => (Z:C) ) = (0.0:0.0:0.0, 0.0:0.0:0.0);
if(D)
  (posedge D => (Z:D) ) = (0.0:0.0:0.0, 0.0:0.0:0.0);
if(!D)
  (negedge D => (Z:D) ) = (0.0:0.0:0.0, 0.0:0.0:0.0);
if(E)
  (posedge E => (Z:E) ) = (0.0:0.0:0.0, 0.0:0.0:0.0);
if(!E)
  (negedge E => (Z:E) ) = (0.0:0.0:0.0, 0.0:0.0:0.0);
if(F)
  (posedge F => (Z:F) ) = (0.0:0.0:0.0, 0.0:0.0:0.0);
if(!F)
  (negedge F => (Z:F) ) = (0.0:0.0:0.0, 0.0:0.0:0.0);
if(G)
  (posedge G => (Z:G) ) = (0.0:0.0:0.0, 0.0:0.0:0.0);
if(!G)
  (negedge G => (Z:G) ) = (0.0:0.0:0.0, 0.0:0.0:0.0);
if(H)
  (posedge H => (Z:H) ) = (0.0:0.0:0.0, 0.0:0.0:0.0);
if(!H)
  (negedge H => (Z:H) ) = (0.0:0.0:0.0, 0.0:0.0:0.0);
if(I)
  (posedge I => (Z:I) ) = (0.0:0.0:0.0, 0.0:0.0:0.0);
if(!I)
  (negedge I => (Z:I) ) = (0.0:0.0:0.0, 0.0:0.0:0.0);
endspecify

endmodule
`endcelldefine