Information: Updating design information... (UID-85) **************************************** Report : timing -path full -delay max -max_paths 1 Design : or1200_alu Version: B-2008.09-SP4 Date : Tue Oct 19 14:27:18 2010 **************************************** * Some/all delay information is back-annotated. Operating Conditions: typical Library: typical Wire Load Model Mode: Inactive. Startpoint: b[1] (input port) Endpoint: result[16] (output port) Path Group: default Path Type: max Point Incr Path ----------------------------------------------------------- input external delay 0.00 0.00 r b[1] (in) 0.03 0.03 r U2577/Y (INVX8) 0.04 * 0.07 f U1151/Y (INVX8) 0.10 * 0.17 r U831/Y (NOR2BX4) 0.05 * 0.23 f U1850/Y (AOI21X4) 0.09 * 0.32 r U1803/Y (CLKINVX4) 0.04 * 0.36 f U1285/Y (OAI2BB1X4) 0.12 * 0.47 f U2559/Y (NAND2X4) 0.07 * 0.54 r U1666/Y (NAND2X4) 0.08 * 0.61 f U1667/Y (AOI21X4) 0.12 * 0.74 r U1111/Y (BUFX20) 0.13 * 0.87 r U1112/Y (INVX4) 0.05 * 0.91 f U2500/Y (NAND2X4) 0.05 * 0.96 r U2501/Y (NAND2X2) 0.04 * 1.00 f U1208/Y (NAND2X2) 0.07 * 1.07 r U1210/Y (NAND3X4) 0.09 * 1.16 f U2938/Y (NOR2X4) 0.09 * 1.25 r U2837/Y (NAND2X4) 0.03 * 1.28 f U663/Y (BUFX8) 0.08 * 1.36 f result[16] (out) 0.00 * 1.36 f data arrival time 1.36 max_delay 1.32 1.32 output external delay 0.00 1.32 data required time 1.32 ----------------------------------------------------------- data required time 1.32 data arrival time -1.36 ----------------------------------------------------------- slack (VIOLATED) -0.04 1