/*************************************************************************/ /* */ /* RC values have been extracted from TSMC's worst case interconnect */ /* tables included with spice model version 1.10. */ /* Document No. TA-10A5-6001 (T-018-LO-SP-001) Rev1.10 Nov 23, 2001 */ /* */ /* Resistance and Capacitance Values */ /* --------------------------------- */ /* The Apollo technology files included in this directory contain */ /* resistance and capacitance (RC) values for the purpose of timing */ /* driven place & route. Please note that the RC values contained in */ /* this tech file were created using the worst case interconnect models */ /* from the foundry and assume a full metal route at every grid location */ /* on every metal layer, so the values are intentionally very */ /* conservative. It is assumed that this technology file will be used */ /* only as a starting point for creating initial timing driven place & */ /* route runs during the development of your own more accurate RC */ /* values, tailored to your specific place & route environment. AS A */ /* RESULT, TIMING NUMBERS DERIVED FROM THESE RC VALUES MAY BE */ /* SIGNIFICANTLY SLOWER THAN REALITY. */ /* */ /* The RC values used in the Apollo technology file are to be used only */ /* for timing driven place and route. Due to accuracy limitations, */ /* please do not attempt to use this file for chip-level RC extraction */ /* in conjunction with your sign-off timing simulations. For chip-level */ /* extraction, please use a dedicated extraction tool such as starRC, */ /* HyperExtract or Simplex, etc. */ /* */ /*************************************************************************/ /* $Id: tsmc18_6lm.tf,v 1.23 2004/04/21 23:11:14 vikas Exp $ */