#################################################################################### # IC Compiler Reference Methodology Release Notes # Version: D-2010.03-SP3 (August 16, 2010) # Copyright (C) 2007-2010 Synopsys All rights reserved. #################################################################################### D-2010.03-SP3 ============= This section describes new features, changes, and enhancements in the IC Compiler Reference Methodology version D-2010.03-SP3. Multicorner-Multimode Updates ----------------------------- All the clock-tree-synthesis-only scenarios are now disabled by default at the beginning of each step except clock_opt_cts in the IC Compiler Reference Methodology flow. * The "set_active_scenarios -all" command at the beginning of each step has been updated as follows: set_active_scenarios [lminus [all_scenarios] [get_scenarios -setup false -hold false -cts_mode true]] ## Note: CTS only scenarios (get_scenarios -setup false -hold false -cts_mode true) are made inactive by RM during optimizations * Synopsys Technical Action Request (STAR) number 9000402453, "implementation change suggested if CTS_ONLY scenarios exist," has been resolved. Clock Tree Synthesis Updates ---------------------------- Support has been added for clock shielding. This feature is turned off by default. To enable it, set ICC_CTS_SHIELD_MODE to ALL or NAMES in icc_setup.tcl. * Use "ALL" to apply the rule specified by $ICC_CTS_SHIELD_RULE_NAME to all the clocks in the design. * Use "NAMES" to apply the rule specified by $ICC_CTS_SHIELD_RULE_NAME to the clock nets specified by $ICC_CTS_SHIELD_CLK_NAMES only. The following files have been updated: * In icc_setup.tcl, new clock-shielding-related variables have been added. The variable names all begin with the "ICC_CTS_SHIELD_" prefix: o ICC_CTS_SHIELD_MODE Use this variable to enable clock shielding for all clocks or for the subset of clocks that you specify with the ICC_CTS_SHIELD_CLK_NAMES variable. o ICC_CTS_SHIELD_RULE_NAME Use this variable to specify the name of the clock shielding rule. o ICC_CTS_SHIELD_SPACINGS Use this variable, which is required by ICC_CTS_SHIELD_RULE_NAME, to specify the clock shield spacing with a list of layer name and spacing pairs. o ICC_CTS_SHIELD_WIDTHS Use this variable, which is required by ICC_CTS_SHIELD_RULE_NAME, to specify the clock shield widths with a list of layer name and width pairs. o ICC_CTS_SHIELD_CLK_NAMES Use this variable, which is required if you set ICC_CTS_SHIELD_MODE to NAMES, to specify the names of the clocks on which you want the shielding rule to be applied. * In common_cts_settings_icc.tcl, a clock shielding nondefault routing rule has been added. * In clock_opt_route_icc.tcl, a command has been added to generate clock shielding wires based on the clock shielding nondefault routing rule. Chip Finishing Update --------------------- The signal electromigration (EM) fix section has been updated. * The commands and examples for the signal electromigration fix flow have been revised. Uncomment the EM section to use the signal electromigration fix feature. * The chip_finish_icc.tcl file has been updated. Timer Updates ------------- * The "set_app_var enable_recovery_removal_arcs true" variable has been moved from pre-clock tree synthesis to post-clock tree synthesis. * The following variable has been added to common_post_cts_timing_settings_icc.tcl: set_app_var enable_recovery_removal_arcs true * The following variable has been removed from common_optimization_settings_icc.tcl: set_app_var enable_recovery_removal_arcs true * STAR number 9000400641, "RM and Lynx mismatch for timer settings post CTS," has been resolved. D-2010.03-SP2 ============= This section describes new features, changes, and enhancements in the IC Compiler Reference Methodology version D-2010.03-SP2. * Multicore support for all the core commands has been added through the "set_host_options -max_cores $ICC_NUM_CORES" command. This command has been consolidated and now appears only in common_optimization_settings_icc.tcl, which is sourced at every step starting with place_opt_icc. o The "set_host_options -max_cores $ICC_NUM_CORES" command that was previously located in common_route_si_settings_zrt_icc.tcl is no longer needed and has been removed. O The "-num_cpus $ICC_NUM_CPUS" option has been removed from place_opt and the other placement-related commands. The comments for the icc_setup.tcl variables ICC_NUM_CPUS and ICC_NUM_CORES have been updated. To enable multicore support for core commands on the local host, set ICC_NUM_CORES to a number that is larger than 1. If you are using the classic router-based flow, you can set ICC_NUM_CPUS to a number that is larger than 1 to enable distributed processing for route_opt and insert_redundant_via. * The redundant via insertion flow has been updated. The redundant via insertion command for clock_opt_route_icc step, "set_route_zrt_common_options -post_detail_route_redundant_via_insertion medium," has been removed. A "Define double vias NDR" example and comments for clock nets have been added to common_cts_settings_icc.tcl. You can follow this example to define double via nondefault routing rules for clock nets. D-2010.03-SP1 ============= This section describes new features, changes, and enhancements in the IC Compiler Reference Methodology version D-2010.03-SP1. Note: The D-2010.03-SP1 version of the IC Compiler Reference Methodology is compatible with IC Compiler version D-2010.03-SP1-1. Multicorner-Multimode and Multimode Clock Tree Synthesis Related Updates ------------------------------------------------------------------------ * The variables ICC_MCMM_CTS_SCENARIO and ICC_MCMM_CTS_SCENARIO_IS_UNIQUE have been removed. To replace them, the mcmm.scenarios.example script has been updated with additional comments on the use of set_scenario_options. To specify clock tree synthesis scenarios, follow the instructions in mcmm.scenarios.example: o To specify a scenario as a clock tree synthesis scenario, use the "set_scenario_options -cts_mode true" command. o To specify a scenario as a clock tree synthesis unique scenario, use the "set_scenario_options -cts_mode true -setup false -hold false" command. Consequently, in the clock_opt_cts_icc and clock_opt_route_icc steps, o The "get_scenarios -cts_mode true" command is used to detect clock tree synthesis scenarios. o The "get_scenarios -cts_mode true -setup false -hold false" command is used to detect clock tree synthesis unique scenarios. * For each step, if the step-specific scenario variable is not specified, all scenarios are activated by default. For example, in the place_opt_icc step, if $ICC_MCMM_PLACE_OPT_SCENARIOS is not specified in icc_setup.tcl, the "set_active_scenarios -all" command is executed at the beginning of the step. This means all the scenarios specified by your $ICC_MCMM_SCENARIO_FILE variable are active. Use step-specific scenario variables, such as $ICC_MCMM_PLACE_OPT_SCENARIOS, to customize the active scenarios for each step. * The ICC_CLOCK_OPT_MCCTO variable has been removed. To specify a scenario for multimode clock tree optimization, use the "set_scenario_options -cts_corner string" command as instructed in mcmm.scenarios.example. * All the get_cts_scenario commands in the scripts have been replaced with "get_scenario_options -cts_mode true" commands. Leakage Power Optimization Updates ---------------------------------- The flow that constrains the percentage of low threshold voltage cells without considering the overall leakage power costs for leakage power optimization has been added in the place_opt_icc, clock_opt_psyn_icc, and route_opt_icc steps. * By default, when you enable leakage optimization, by setting $LEAKAGE_POWER to TRUE, the traditional leakage optimization flow is still used. * To constrain the percentage of low threshold voltage cells without considering the overall leakage power costs for leakage power optimization, uncomment and edit the section "%LVT leakage power optimization flow (edit before using it)" in the scripts. UPF Updates ----------- * Support has been added for the low power implementation flow. New variables, ICC_UPF_PM_CELL_EXISTING and ICC_UPF_PM_CELL_INSERTION, have been added to icc_setup.tcl. o Use ICC_UPF_PM_CELL_EXISTING to specify whether the design contains preexisting power management cells. If ICC_UPF_PM_CELL_EXISTING is set to TRUE, it runs the associate_mv_cells command. You should review the reports before proceeding. o Set ICC_UPF_PM_CELL_INSERTION to TRUE to run the insert_mv_cells command. Placement Optimization (place_opt) Related Updates -------------------------------------------------- * Comments have been added regarding saving the environment for the consistency checker utility. For more details, see SolvNet article number 026366. * Comments have been updated in the relative placement section. * Physical guidance flow support has been added. A new option, Physical Guidance, has been added to RMgen on SolvNet. Set this option to TRUE if you want to use physical guidance information from Design Compiler Graphical. The UPF, feasibility, and time to results (TTR) configurations are not supported in the physical guidance flow. In RMgen, when you set the Physical Guidance option to TRUE, do not select the UPF, FEASIBILITY, or TTR settings. Note: To generate the physical guidance information by using the Design Compiler Reference Methodology, you must also set the Physical Guidance option to TRUE when you generate Design Compiler Reference Methodology scripts. After downloading the generated scripts, o You must not add commands that modify the netlist or floorplan in the init_design_icc and place_opt_icc steps before the "place_opt -spg" command is run. o You must use a binary design format, Synopsys logical database format (.ddc) or Milkyway, from the Design Compiler Reference Methodology output. This means the $ICC_INIT_DESIGN_INPUT == "Verilog" flow is not supported and has been omitted. o You must use a floorplan from the Design Compiler Reference Methodology output, such as a Design Exchange Format (DEF) file. The $ICC_FLOORPLAN_INPUT == "CREATE" and $ICC_FLOORPLAN_INPUT == "FP_FILE" flows are not supported and have been omitted. * The -area_recovery option has been added to the place_opt_feasibility command. Clock Tree Synthesis Related Updates ------------------------------------ * The core commands in the clock_opt_cts step have been updated with the use of the lappend command. * For $ICC_CTS_INTERCLOCK_BALANCING, a condition has been added that checks the existence of $ICC_CTS_INTERCLOCK_BALANCING_OPTIONS_FILE before enabling the -inter_clock_balance option for the clock_opt command. * Support has been added for the clock_opt_feasibility command. If you select FEASIBILITY for the "Focus on TTR or QoR or Feasibility" option in RMgen, the clock_opt_feasibility command is used in the clock_opt_psyn step. Chip Finishing Related Updates ------------------------------ * For the Zroute flow, the concurrent redundant via insertion setting "set_route_zrt_common_options -concurrent_redundant_via_mode reserve_space" in common_route_si_(zrt)_settings_icc.tcl has been moved to route_icc.tcl prior to the route_opt command. This setting now requires the $ICC_DBL_VIA_FLOW_EFFORT == "HIGH" variable setting. If it is enabled before route_opt, it is disabled automatically after route_opt. * For antenna prevention, "remove_attribute $ICC_PORT_PROTECTION_DIODE dont_use" has been added before the insert_port_protection_diodes command in the clock_opt_psyn step. * A check has been added in chip_finish_icc and signoff_opt_icc steps to see if the list is empty before running insert_stdcell_filler on $FILLER_CELL_METAL or $FILLER_CELL. Signoff Related Updates ----------------------- Support for the check_signoff_correlation command has been added in the place_opt_icc and route_opt_icc steps. Two new variables have been added to icc_setup.tcl. * Specify ICC_SIGNOFF_OPT_CHECK_CORRELATION_PREROUTE_SCRIPT to allow sourcing of your script of choice at the end of the place_opt_icc step. The script should contain your desired set_primetime_options, set_starcxt_options, and "check_signoff_correlation -preroute" commands. You can use the signoff_opt_check_correlation_preroute_icc.example.tcl as a starting point. * Specify ICC_SIGNOFF_OPT_CHECK_CORRELATION_POSTROUTE_SCRIPT to allow sourcing of your script of choice at the end of the route_opt_icc step. The script should contain your desired set_primetime_options, set_starcxt_options, and check_signoff_correlation commands. You can use the signoff_opt_check_correlation_postroute_icc.example.tcl as a starting point. Miscellaneous Updates --------------------- * The read_sdc command in init_design_icc step has been moved from before load_upf to after load_upf. * The common_post_cts_timing_settings.tcl file has been updated. o The line "remove_attribute $ICC_FIX_HOLD_PREFER_CELLS dont_use" has been removed because it is no longer needed. o The line "set_fix_hold_options -preferred_buffer" has been added to allow hold fix to ignore the dont_use attribute. Hold fix now ignores the dont_use attribute automatically. * Support has been added for the categorized timing report. The query_qor_snapshot command has been added in comments at the end of the place_opt_icc and clock_opt_pysn_icc steps. D-2010.03 ========= This section describes new features, changes, and enhancements in the IC Compiler Reference Methodology version D-2010.03. Lynx Compatibility ------------------ This release introduces Lynx-compatible versions of the reference methodology scripts, which you can select in RMgen on SolvNet. For more information about the Lynx-compatible reference methodology scripts, see SolvNet article number 029774 at https://solvnet.synopsys.com/retrieve/029774.html. Directory Structure Changes --------------------------- The reference methodology directory structure has been reorganized for all versions of the product reference methodologies. * The setup files and makefiles have been moved to a new directory named rm_setup. * The scripts directory has been renamed rm__scripts, where is the product identifier: dc, icc, pt, or tmax. These changes are the same for every product reference methodology and apply to both the standard and Lynx-compatible versions of the reference methodology scripts. The working directory structure depends on whether you are using standard reference methodology scripts or Lynx-compatible reference methodology scripts. Due to the directory structure change, the procedure for running the reference methodology scripts has changed from previous releases. For example, to run the IC Compiler Reference methodology scripts, enter % make -f rm_setup/Makefile_zrt ic See README.ICC-RM.txt if you need more details. General Updates --------------- * The DFT Optimization, Dynamic Power Optimization, and Leakage Power Optimization options have been removed from RMgen and converted to icc_setup.tcl variables. You can control whether these optimizations are performed by setting the DFT, DYNAMIC_POWER, and LEAKAGE_POWER variables in icc_setup.tcl. All scripts have been updated. * The read_io_constraints and write_io_constraints commands have been replaced by the read_pin_pad_physical_constraints and write_pin_pad_physical_constraints commands. The init_design_icc.tcl file has been updated. * New variables, PLACE_OPT_EFFORT and ROUTE_OPT_EFFORT, have been added to allow you to control the effort level options for the place_opt and route_opt commands. The default option value is medium. These variables are available only when you select the QOR setting for the "Focus on TTR, QoR, or Feasibility" option in RMgen. * A new variable, PLACE_OPT_CONGESTION, has been added to allow you to control the -congestion option in the place_opt. The default setting is TRUE. This variable is available only when you select the QOR or FEASIBILITY setting for the "Focus on TTR, QoR, or Feasibility" option in RMgen. * Comments for the set_clock_gating_check commands have been added in the init_design_icc.tcl file. Multicorner and Multimode Related Updates ----------------------------------------- * A new variable, ICC_MCMM_CTS_SCENARIO_IS_UNIQUE, has been added to control whether the clock tree synthesis scenario can be optimized by clock tree synthesis only (TRUE) or by clock tree synthesis and other optimization steps (FALSE). * In mcmm.scenarios.example, the examples are now based on on-chip variation (OCV) instead of best-case and worst-case. * The signoff_opt command now supports multicorner and multimode. The signoff_opt_icc.tcl file has been updated to support multicorner and multimode. The report_primetime_options and report_starrcxt_options commands have been added for each scenario in mcmm.scenarios.example. Clock Tree Synthesis Updates ---------------------------- * Interclock delay balancing has been moved from clock_opt_cts_icc.tcl to init_design_icc.tcl. * When ICC_REPORTING_EFFORT is set to low, the report_qor, report_constraints, and report_timing commands are skipped during the clock_opt_cts stage. The clock_opt_cts_icc.tcl file has been updated. * In previous releases, selecting TTR for the ICC_STRATEGY option in RMgen caused a different setting to be used in set_delay_calculation. This difference has now been removed. The icc_scripts/clock_opt_route_icc.tcl file has been updated. * For the classic router flow, route_group has been added after "clock_opt -only_psyn" to exit the clock tree synthesis frozen skew mode. The clock_opt_psyn_icc.tcl file has been updated. * Comments have been added to set_clock_tree_options to control the max_transition, max_capacitance, and target_skew options. The common_cts_settings_icc.tcl file has been updated. Zroute Updates -------------- For the Zroute-based flow, the "set_route_mode_options -zroute true" command has been removed from the following files in the icc_zrt_scripts directory because Zroute is now enabled by default: * clock_opt_route_icc.tcl * route_icc.tcl * route_opt_icc.tcl For the classic router flow, the "set_route_mode_options -zroute false" command has been added to the following files in the icc_scripts directory to explicitly disable Zroute. * clock_opt_route_icc.tcl * route_icc.tcl * route_opt_icc.tcl The makefiles, Makefile_zrt and Makefile, are still used to run the Zroute-based and classic router-based reference methodology scripts respectively. For general information about the tool invocation, see README.ICC-RM.txt. Updates Related to the route_icc, route_opt_icc, and chip_finish_icc steps -------------------------------------------------------------------------- * New controls for crosstalk reduction have been added in rm_icc_zrt_scripts/common_route_si_settings_icc.tcl. This includes the set_route_opt_zrt_crosstalk_options command syntax and examples. * The "set_app_var psyn_onroute_disable_fanout_drc true" command has been removed from common_route_si_settings_icc.tcl in both rm_icc_scripts and rm_icc_zrt_scripts. * The snapshot command at the end of route_icc.tcl has been changed to gui_write_window_image. * The route_opt command usage has been updated. Comments have been added regarding control of power-aware optimization and power recovery. The route_opt_icc.tcl file has been updated. * Comments on reshielding in rm_icc_zrt_scripts/chip_finish_icc.tcl have been updated for the "set_route_zrt_common_options -reshield_modified_nets reshield" command. Updates for focal_opt Command Usage ----------------------------------- * The focal_opt command is now a standalone step. Previously, it was part of the chip_finish step. The following files have been updated: o Makefiles o chip_finish_icc.tcl o focal_opt_icc.tcl The ICC_FOCAL_OPT variable has been removed from icc_setup.tcl and the scripts. * The following new variables have been added in icc_setup.tcl to control the focal_opt options -drc_nets, -drc_pins, and -xtalk_reduction: o ICC_FOCAL_OPT_DRC_NET_VIOLS o ICC_FOCAL_OPT_DRC_PIN_VIOLS o ICC_FOCAL_OPT_XTALK_VIOLS * Because focal_opt is now an independent step, you can control the starting CEL view and saved CEL view names by using the following new variables: o ICC_FOCAL_OPT_STARTING_CEL, which defaults to $ICC_CHIP_FINISH_CEL o ICC_FOCAL_OPT_CEL. Metal Fill Related Updates -------------------------- * The signoff_metal_fill support has been removed for -timing_preserve_hold_slack_threshold $TIMING_PRESERVE_SLACK_HOLD. The metal_fill_icc.tcl and icc_setup.tcl files have been updated. * The set_extraction_options command in metal_fill_icc.tcl has been updated. The value used by the -real_metalfill_extraction option is set to FLOATING before the "save_mw_cel -as $ICC_METAL_FILL_CEL" command. If the $ICC_METAL_FILL_TIMING_DRIVEN variable is set to TRUE, the -real_metalfill_extraction option is set to NONE before the metal fill insertion command runs and is then reset to FLOATING when metal fill insertion has been completed. Updates That Affect the write_verilog Options and Comments ---------------------------------------------------------- * The outputs_icc.tcl file has been updated. * The "-pg -supply_statement none" options are used if design is UPF. * Different outputs are generated for use with Formality, layout versus schematic (LVS), and comparison with a Design Compiler netlist. Updates for create_ilm Command Usage ------------------------------------ The following files have been updated: * In outputs_icc.tcl, there is now no difference in the commands used for the UPF and non-UPF flows. Comments have been added for the -scenario option, the write_interface_timing command, and the compare_interface_timing command. * In prepare_block_dp.tcl, comments have been added to the select_block_scenario command and removed from the -include_xtalk option. * In init_design_icc.tcl, a select_block_scenario comment has been added. Engineering Change Order (ECO) Updates -------------------------------------- The variables ICC_PRE_ECO_CEL and ICC_POST_ECO_CEL in icc_setup.tcl have been renamed to ICC_ECO_STARTING_CEL and ICC_ECO_CEL respectively. New Flip Chip Flow for Flat Design Support ------------------------------------------ Set the Flip Chip Design Style option to TRUE in RMgen if you want the generated scripts to include flip chip support. For more information about the flip chip flow, see SolvNet article number 025348 A new file, rm_icc_dp_scripts/flip_chip.tcl, contains all the flip chip flow steps. The following files have been enhanced: * In init_design_icc.tcl, sourcing of flip_chip.tcl has been added. * In icc_setup.tcl, new variables with the prefix ICC_FLIP_CHIP_ have been added. New Formality Verification Flow Support --------------------------------------- Formality performs verification of the netlist going into IC Compiler versus the Verilog netlist created by IC Compiler. A new file, rm_icc_scripts/fm.tcl, runs Formality after the outputs_icc step is completed. Enter the following command to run Formality: % fm_shell -f rm_icc_scripts/fm.tcl | tee log_zrt/fm.log (or log/fm.log) New Step-Specific Reporting Directories --------------------------------------- New variables, REPORTS_DIR_*, have been added for step-specific reporting directories. If you want to have a specific report directory for each step, use the REPORTS_DIR_* variables instead of the REPORTS_DIR variable. By default, the tool writes all the reports to REPORTS_DIR and there is no impact on existing usage. The icc_setup.tcl file and all scripts have been updated. New Checkpoint Strategy Support ------------------------------- Support has been added for set_checkpoint_strategy through a new variable, ICC_ENABLE_CHECKPOINT, in icc_setup.tcl. When this variable is set to true, set_checkpoint_strategy is applied to the place_opt, clock_opt_cts, clock_opt_psyn, and route_opt stages. Please ensure there's enough disk space before enabling this feature. The -overwrite option is used by default. Remove it if needed. C-2009.06-SP4 ============= This section describes new features, changes, and enhancements in the IC Compiler Reference Methodology version C-2009.06-SP4. * Support has been added for the new feasibility flow. To enable the feasibility flow in RMgen, select the FEASIBILITY setting for the "Focus on TTR, QoR, or Feasibility" option. The following scripts have been enhanced: o icc_scripts/place_opt_icc.tcl The feasibility flow uses the "place_opt_feasibility -congestion" command. o icc_scripts/clock_opt_psyn_icc.tcl The feasibility flow uses the "clock_opt -no_clock_route -only_psyn" command. o icc_scripts/route_icc.tcl (if the classic router is used) or icc_zrt_scripts/route_icc.tcl (if Zroute is used) The feasibility flow uses the "route_opt -initial_route_only -stage track" command and skips the double via insertion step. o Makefile (if the classic router is used) or Makefile_zrt (if Zroute is used) The feasibility flow ends at the route_icc step. * A new IC Compiler Reference Methodology variable, ICC_LOW_POWER_PLACEMENT, has been added. If you set this variable to true, the -power option is enabled in the place_opt command for the place_opt_icc stage and in the clock_opt command for the clock_opt_cts stage. * The link command has been removed in icc_scripts/init_design_icc.tcl for cases when ICC_INIT_DESIGN_INPUT is set to VERILOG because it is no longer needed. * The derive_pg_connection command usage for the UPF configuration has been updated in icc_scripts/init_design_icc.tcl. The "derive_pg_connection -verbose" and "derive_pg_connection -verbose -tie" commands have been moved to follow the "source -echo $CUSTOM_POWER_SWITCH_SCRIPT" command. Previously, they followed the "derive_pg_connection -create_net" command. * The derive_pg_connection command usage for the UPF configuration has been updated as follows: The "derive_pg_connect -tie -verbose" command is performed if $CUSTOM_CONNECT_PG_NETS_SCRIPT is not provided and $ICC_TIE_CELL_FLOW is FALSE. Changes have been made in the following scripts: o icc_scripts/place_opt_icc.tcl o icc_scripts/clock_opt_cts_icc.tcl o icc_scripts/clock_opt_psyn_icc.tcl o icc_scripts/clock_opt_route_icc.tcl o icc_scripts/route_opt_icc.tcl o icc_scripts/chip_finish_icc.tcl o icc_scripts/signoff_opt_icc.tcl o icc_scripts/eco_icc.tcl o icc_zrt_scripts/clock_opt_psyn_icc.tcl o icc_zrt_scripts/clock_opt_route_icc.tcl o icc_zrt_scripts/route_opt_icc.tcl o icc_zrt_scripts/chip_finish_icc.tcl o icc_zrt_scripts/signoff_opt_icc.tcl o icc_zrt_scripts/eco_icc.tcl * The example icc_scripts/mcmm.scenarios.example has been updated as follows: o The set_active_scenario command has been removed. o The report_scenario_options command appears only once. o The example for the set_scenario_options command has been updated. * The "set_app_var verilogout_no_tri true" command has been removed in icc_scripts/outputs_icc.tcl and icc_zrt_scripts/outputs_icc.tcl because it is obsolete. C-2009.06-SP3 ============= This section describes new features, changes, and enhancements in the IC Compiler Reference Methodology version C-2009.06-SP3. * For multivoltage checking completeness, the "check_mv_design -power -verbose" command has been replaced by the "check_mv_design -verbose" command throughout the UPF flow. Changes have been made in the following scripts: icc_scripts/place_opt_icc.tcl icc_scripts/clock_opt_cts_icc.tcl icc_scripts/clock_opt_psyn_icc.tcl icc_scripts/clock_opt_route_icc.tcl icc_scripts/route_icc.tcl icc_scripts/route_opt_icc.tcl icc_scripts/chip_finish_icc.tcl icc_scripts/signoff_opt_icc.tcl icc_scripts/metal_fill_icc.tcl icc_scripts/eco_icc.tcl icc_zrt_scripts/clock_opt_psyn_icc.tcl icc_zrt_scripts/clock_opt_route_icc.tcl icc_zrt_scripts/route_icc.tcl icc_zrt_scripts/route_opt_icc.tcl icc_zrt_scripts/chip_finish_icc.tcl icc_zrt_scripts/signoff_opt_icc.tcl icc_zrt_scripts/metal_fill_icc.tcl icc_zrt_scripts/eco_icc.tcl * The following changes have been made in icc_scripts/init_design_icc.tcl: o The set_clock_gating_check command has been updated from [all_clocks] to [current_design]. This command is now always run. Previously, it was commented. o Comments have been added to the set_timing_derate commands to remind you that if you are adding customized set_timing_derate commands for lib cells, you should add them for every step in the flow. * Variable names in icc_setup.tcl and icc_(zrt)_scripts/signoff_opt_icc.tcl have been updated to use the STARRC prefix instead of STARRCXT. * The following changes have been made in icc_scripts/clock_opt_cts_icc.tcl: o For clock gate merging (ICC_CTS_CLOCK_GATE_MERGE), the optimize_pre_cts_power command has been removed because it is no longer needed. o For clock gate splitting (ICC_CTS_CLOCK_GATE_SPLIT), the split_clock_gates commands have been removed because they are no longer needed. The "set_optimize_pre_cts_power_options -split true" command is used instead. o The clock tree synthesis scenario is now included for report_clock_tree reporting and excluded for report_timing reporting. o Clock reconvergence pessimism removal (CRPR) is now applied by sourcing common_post_cts_timing_settings.tcl after the "clock_opt -cts_only" core command has completed. o The following Synopsys Technical Action Request (STAR) has been resolved: 9000345645: RM alters design state only * The create_ilm command has been updated in icc_(zrt)_scripts/outputs_icc.tcl for the UPF flow. The options -compact none and -traverse_disabled_arcs are no longer needed and have been removed. C-2009.06-SP2 ============= This section describes new features, changes, and enhancements in the IC Compiler Reference Methodology version C-2009.06-SP2. * The following new feature has been added: o IC Validator integration has been added for timing-driven signoff metal fill. To enable this feature, use the new variable SIGNOFF_METAL_FILL_TIMING_DRIVEN. To control the preservation of timing-critical nets, use the new variables TIMING_PRESERVE_SLACK_SETUP and TIMING_PRESERVE_SLACK_HOLD. Changes have been made in icc_scripts/metal_fill_icc.tcl and icc_zrt_scripts/metal_fill_icc.tcl. * The following feature has been updated: o The user interface for wire spreading and widening has been enhanced. The variable TIMING_PRESERVE_SLACK has been replaced by the variables TIMING_PRESERVE_SLACK_SETUP and TIMING_PRESERVE_SLACK_HOLD. To control the preservation of timing-critical nets, use the new variables TIMING_PRESERVE_SLACK_SETUP and TIMING_PRESERVE_SLACK_HOLD. Changes have been made in icc_scripts/chip_finish_icc.tcl and icc_zrt_scripts/chip_finish_icc.tcl. * The following new IC Compiler Reference Methodology variables have been added: o SIGNOFF_METAL_FILL_TIMING_DRIVEN o TIMING_PRESERVE_SLACK_SETUP o TIMING_PRESERVE_SLACK_HOLD * The following IC Compiler Reference Methodology variable is now obsolete: o TIMING_PRESERVE_SLACK C-2009.06-SP1 ============= This section describes new features, changes, and enhancements in the IC Compiler Reference Methodology version C-2009.06-SP1. * New features o Clock gate merging as an additional way to reduce dynamic power o Clock gate splitting to avoid timing violations on the enable pin of the clock gates o Weight-based redundant via insertion in Zroute o Automatically derive power and ground connections for UPF. o New always-on synthesis, which is enabled by default o Value checking of the reference methodology variables in the icc_setup.tcl file o Incremental shielding flow with Zroute o End cap cell insertion, including insertion of vertical end caps (well-proximity effect) o Creation of the global route congestion map in PNG format * Updated features o Capability to define your own options for the IC Compiler insert_metal_filler command o New user interface for insert_spare_cells when defining different amounts of the different types of cells to be inserted o Constrained decoupling capacitor insertion using insert_stdcell_filler o Streamlined multicorner-multimode commands: -- Removed redundant post-clock tree synthesis set_active_scenario commands prior to report_timing in init_design_design.tcl and clock_opt_cts_icc.tcl -- Restored the scenarios that were defined prior to clock tree synthesis (all_scenarios is enabled just before clock tree synthesis) * New IC Compiler Reference Methodology variables: o ICC_CREATE_GR_PNG o ICC_CTS_CLOCK_GATE_MERGE o ICC_CTS_CLOCK_GATE_SPLIT o ICC_H_CAP_CEL o ICC_V_CAP_CEL o ICC_MCMM_METAL_FILL_SCENARIOS o ICC_METAL_FILL_SPACE o ICC_METAL_FILL_TIMING_DRIVEN C-2009.06 ========= This section describes new features, changes, and enhancements in the IC Compiler Reference Methodology version C-2009.06. * New features o Postroute clock tree optimization: -- For both regular flow and multicore clock tree optimization -- Use the new variable ICC_POST_CLOCK_ROUTE_CTO = TRUE o IC Validator integration: -- For both metal fill and DRC -- Use the following variables to control these features: set ADD_METAL_FILL "ICV" set SIGNOFF_FILL_RUNSET "" ;# runset for signoff_metal_fill set SIGNOFF_DRC_ENGINE "ICV" ;# ICV | HERCULES set SIGNOFF_DRC_RUNSET "" ;# runset for signoff_drc set SIGNOFF_MAPFILE "" ;# Mapping file for signoff_metal_fill|signoff_drc o Multicore support for extraction, Zroute, and multicorner and multimode timing analysis: This is controlled by the variable ICC_NUM_CORES> o ECO flow: Both unconstrained and silicon freeze ECO flows are supported. Use the following variables: set ICC_ECO_FLOW "UNCONSTRAINED" ;# NONE|UNCONSTRAINED|FREEZE_SILICON ;# UNCONSTRAINED : NO spare cell insertion ; cells can be added (pre-tapeout) ;# FREEZE_SILICON : spare cell insertion/freeze silicon ECO set ICC_SPARE_CELL_FILE "" ;# Tool command language (Tcl) script to insert the spare cells ;# insert_spare_cells -lib_cell {INV8 DFF1} -cell_name spares - num_instances 300 set ICC_ECO_NETLIST "" ;# New Verilog netlist containing the ECO changes set ICC_PRE_ECO_CEL $ICC_SIGNOFF_OPT_CEL ;# CEL view to run ECO on (contains original pre-tapeout database) set ICC_POST_ECO_CEL "eco_icc" ;# CEL view after running the ECO (contains new eco netlist) * Updated features o Double Via insertion, for Zroute only: -- Three flows are available, controlled by the new variable ICC_DBL_VIA_FLOW_EFFORT -- Set this variable to LOW (the default), MED, or HIGH LOW: The default flow, identical to B-2008.09-SP5 routing + via doubling + route_opt MED: Routing with space reservation + via doubling + route_opt HIGH: Medium flow + timing-driven via doubling with high effort at the end of chip finishing o Arnoldi: -- Use the IC Compiler Reference Methodology variable ICC_FULL_ARNOLDI to enable full Arnoldi (default = false) o No extra manual command for derive_pg_connection for physical only cells o focal_opt is more data driven, controlled by the following variables: set ICC_FOCAL_OPT TRUE ;# TRUE|FALSE : enables the focal_opt command at the end of chip finishing set ICC_FOCAL_OPT_HOLD_VIOLS "" ;# filename containing the hold violations set ICC_FOCAL_OPT_SETUP_VIOLS "" ;# filename containing the SETUP violations set ICC_FOCAL_OPT_DRC_VIOLS "" ;# filename containing the DRC violations o Multicorner and multimode: -- New UI for set_scenario_options -- You no longer need to make all scenario's active prior to ILM creation o Metal fill flow -- Changed the location of the metal fill flow; it is now used after signoff_opt in a separate script * Resolved STARs: o 9000286311: MWUI-040: Cannot modify attribute on object o 9000315543: TTR flow sets clock_arnoldi o 9000315542: timing setup in COMMAND section of RMgen o 9000315738: LEAKAGE_POWER modal variable behavior change * New IC Compiler Reference Methodology variables: o ICC_CUSTOM_DBL_VIA_DEFINE_SCRIPT o ICC_DBL_VIA_FLOW_EFFORT o ICC_ECO_NETLIST o ICC_FOCAL_OPT o ICC_FOCAL_OPT_DRC_VIOLS o ICC_FOCAL_OPT_HOLD_VIOLS o ICC_FOCAL_OPT_SETUP_VIOLS o ICC_ECO_FLOW o ICC_FULL_ARNOLDI o ICC_METAL_FILL_CEL o ICC_NUM_CORES o ICC_POST_CLOCK_ROUTE_CTO o ICC_POST_ECO_CEL o ICC_PRE_ECO_CEL o ICC_SPARE_CELL_FILE o SIGNOFF_DRC_ENGINE * Obsolete IC Compiler Reference Methodology variables: o ICC_NUM_THREADS o AO_MODE B-2008.09-SP5 ============= This section describes new features, changes, and enhancements in the IC Compiler Reference Methodology version B-2008.09-SP5. * New features: o Tie cell flow o Interclock delay balancing and update clock latency: now integrated and controlled by four variables o Uncertainty management o Design validation with check_physical_design o Usage of all_level_shifter plus all_ao_cells instead of the two IC Compiler Reference Methodology variables * Updated features: o Introduced the ICC_MAX_AREA variable to specify the max_area constraint for area optimization. o Changed the location of the CUSTOM_DECONDARY_POWER_ROUTE_SCRIPT file. o Added tags for opening and closing the scripts. o Replaced hard-coded values with new IC Compiler Reference Methodology variables for max_transition and critical_range. o Updated the multicorner-multimode flow to avoid unnecessary changes of active scenarios. * Resolved STARs: o 9000288392: ICDB and clock-latency adjustment rules to be MCMM-aware o 9000277452: Suppressing Warning: overriding result from previous set_ideal_network command o 9000312325: check_error misplaced in Reference Methodology o 9000310034: ICC-RM add routeopt_skip_report_qor set to true to improve runtime o 9000274984: CTS reports being generated outside of CTS-scenario in MCMM mode o 9000303308: Incorrect moving of clock constraint on hierarchical pin o 9000273902: Reference Methodology needs to remove unnecessary scenario changes and updates when not Adaptive o 9000310305: IC Compiler Reference Methodology place_opt_icc.tcl reports for all_scenarios| o 9000263367: Uncertainty management needs to be done before post-CTS opto o 9000269959: place_opt Reference Methodology flow uses -area, but does not set_max_area| o 9000286311: MWUI-040: Cannot modify attribute on object|Reference Methodology o 9000277452: Suppressing Warning: overriding result from previous set_ideal_network command o 9000270743: Reference Methodology no longer uses get_dominant_scenario by default * New IC Compiler Reference Methodology variables: o ICC_APPLY_RM_UNCERTAINTY_PRECTS o ICC_APPLY_RM_UNCERTAINTY_POSTCTS o ICC_UNCERTAINTY_PRECTS_FILE o ICC_UNCERTAINTY_POSTCTS_FILE o ICC_CRITICAL_RANGE o ICC_CTS_INTERCLOCK_BALANCING o ICC_CTS_INTERCLOCK_BALANCING_OPTIONS_FILE o ICC_CTS_LATENCY_OPTIONS_FILE o ICC_CTS_UPDATE_LATENCY o ICC_MAX_AREA o ICC_MAX_FANOUT o ICC_MAX_TRANSITION o ICC_SANITY_CHECK o ICC_TIE_CELL_FLOW * Obsolete IC Compiler Reference Methodology variables : o AO_CELLS o LS_CELLS B-2008.09-SP4 ============= This section describes new features, changes, and enhancements in the IC Compiler Reference Methodology version B-2008.09-SP4. * New features: o Support for hierarchical UPF o Emulated metal fill flow o Placement utilization report command: report_placement_utilization * Updated features: o Leakage optimization flow on by default o Chip finishing: -- Diode insertion on ports during preroute stage to prevent antenna violations. -- Additional variables to control the diodes inserted during routing stage for antenna violations -- Multi-voltage threshold standard cell filler insertion during chip finishing. o Timing Derating: -- Allow use of either the default reference methodology timing derate or the user-defined timing derate from the Synopsys Delay Constraints (SDC) constraints o Signoff Driven Physical verification: -- Map file for signoff_drc to improve flexibility. * STARs fixed: o 9000304029: CUSTOM_CONNECT_PG_NETS_SCRIPT not defined o 9000258143: Add set_tlu_plus -max_emulation_tluplus -min_emulation_tluplus o 9000258142: Add "set_extraction_options -virtual_shield_extraction false" to extract shield o 9000258141: Add set_extraction_options -real_metal_fill_extraction to extract metal fill o 9000299005: IC Compiler Reference Methodology: derive_pg_connection redundant calls with -reconnect option o 9000281426: IC Compiler Hierarchical Reference Methodology: How to read multiple UPF files, one for each block, and one for top o 9000299005: IC Compiler Reference Methodology: derive_pg_connection redundant calls with -reconnect option o 9000298519: Dominant scenario analysis in clock_opt_psyn_icc.tcl * New ICC RM variables: o CUSTOM_CREATE_VA_SCRIPT o ICC_APPLY_RM_DERATING o ICC_EARLY_DERATING_FACTOR o ICC_LATE_DERATING_FACTOR o ICC_PHYSICAL_CONSTRAINTS_FILE o ICC_PORT_PROTECTION_DIODE o ICC_ROUTING_DIODES o ICC_SKIP_IN_BLOCK_IMPLEMENTATION o ICC_USE_DIODES o SIGNOFF_MAPFILE o TLUPLUS_MAX_EMULATION_FILE o TLUPLUS_MIN_EMULATION_FILE B-2008.09-SP3 ============= This section describes new features, changes, and enhancements in the IC Compiler Reference Methodology version B-2008.09-SP3. * Added functionality: o 2X double spacing nondefault routing rules by default for clock nets o New variable, ICC_REPORTING_EFFORT, controls whether any reports are created o Multivoltage-aware standard cell fill * Flow changes: o Change for double via insertion in the Zroute flow o signal_em moved prior to metal filling * New ICC Reference Methodology variables: o ICC_CTS_RULE_NAME o ICC_REPORTING_EFFORT B-2008.09-SP2 ============= This section describes new features, changes, and enhancements in the IC Compiler Reference Methodology version B-2008.09-SP2. * Added functionality: o Additional commands: -- signoff_metal_fill -- signoff_drc -- Focal_opt o Multicorner clock tree optimization o Signal electromigration o Additions to the Zroute flow: -- Double via after clock routing -- Ensure EcoRt is keeping the double vias -- Standard cell metal filler o Additions to the multicorner-multimode flow: -- write_parasitics across all scenarios -- write_sdc across all scenarios -- report_clock_tree across all scenarios * New IC Compiler Reference Methodology variables: o MCCTO_MODE o MCCTO_SCENARIOS o MCCTO_TARGET_SKEWS o SIGNOFF_DRC_RUNSET o SIGNOFF_FILL_RUNSET B-2008.09-SP1 ============= This section describes new features, changes, and enhancements in the IC Compiler Reference Methodology version B-2008.09-SPq. * Extension of the multicorner-multimode flow, in addition to the default adaptive flow. * New user-controlled flow, which allows you to specify different scenarios for the major steps of the flow. B-2008.09 ========= This section describes new features, changes, and enhancements in the IC Compiler Reference Methodology version B-2008.09. * Same functionality, but made use of the new commands in IC Compiler B-2008.09: o Use derive_pg_conn instead of connect_pg_nets o New Verilog reader for the ASCII flow * Functional change for the multicorner-multimode flow and for ideal_net handling. Now an ideal net is iterated over the scenarios. A-2007.12-SP5-1 =============== This section describes new features, changes, and enhancements in the IC Compiler Reference Methodology version A-2007.12-SP5-1. * Added the Zroute flow. * Change to trim_fill_eco: now uses the FILL view. * Removed redundant update_timing commands for multicorner-multimode flows. * Added the remove_cell command to save disk space. A-2007.12-SP4 ============= This section describes new features, changes, and enhancements in the IC Compiler Reference Methodology version A-2007.12-SP4. * Some changes for the multicorner-multimode flows * Change in the timing derating values applied in the flow * Small change to the hierarchical flow A-2007.12-SP3 ============= This section describes new features, changes, and enhancements in the IC Compiler Reference Methodology version A-2007.12-SP3. * Split clock_opt_icc into 3 scripts. * Split route_opt_icc into 2 scripts. * Added the DFT and power optimization flows. * Various changes for the multicorner-multimode flow. * The UPF example that was introduced in version A-2007.12-SP2 is now fully functional. A-2007.12-SP2 ============= This section describes new features, changes, and enhancements in the IC Compiler Reference Methodology version A-2007.12-SP2. * UPF reference methodology: o The complete IC Compiler UPF flow is available. -- Details on how to set this up are provided above. -- Also refer to the live example for the actual details. o Removed the wrong way router settings for clock routing since this is no longer required. * Hierarchical Reference Methodology: o The descriptions for ICC_DP_PLAN_GROUPS and ICC_DP_CTP_ANCHOR_CEL in icc_setup.tcl have been updated. o icc_dp_scripts/hierarchy_dp.tcl has been updated. -- Comments in the clock tree planning section -- Checking for ICC_DP_CTP_ANCHOR_CEL added before set_fp_clock_plan_options o icc_dp_scripts/prepare_block_dp.tcl has been updated: -- Now PNS_BLOCK_MODE is set to true in icc_setup.tcl for subblocks A-2007.12-SP1 ============= This section describes new features, changes, and enhancements in the IC Compiler Reference Methodology version A-2007.12-SP1. * Integrated the physical hierarchical reference methodology, which has a separate application note. * Usage of the check_library command to cross check the logic library versus the physical library added into init_design_icc.tcl. * Usage of the route_opt -incremental -size_only command after chip finishing, instead of the full route_opt command, to avoid too much disturbance to the design. This improves the double via rate. * Expanded the reporting commands for multicorner and multimode. A-2007.12 ========= This section describes new features, changes, and enhancements in the IC Compiler Reference Methodology version A-2007.12. * Integrated the QoR reference methodology, enabled by one simple variable (for details see above). * Some changes involving the multivoltage variables due to an alignment with Design Compiler Reference Methodology version A-2007.12. * Usage of the new automatic switch for double via insertion. Z-2007.03-SP5 ============= This section describes new features, changes, and enhancements in the IC Compiler Reference Methodology version Z-2007.03-SP5. * Changed the usage of CTS_SCENARIO for multicorner and multimode. From now on, this scenario is used only during clock tree synthesis, and is ignored during the optimization steps before or after clock tree synthesis and optimization. Z-2007.03-SP3 ============= This section describes new features, changes, and enhancements in the IC Compiler Reference Methodology version Z-2007.03-SP3. * Added signoff_opt. * Added multithreshold-CMOS for multivoltage. Z-2007.03-SP2 ============= This section describes new features, changes, and enhancements in the IC Compiler Reference Methodology version Z-2007.03-SP2. * Complete revamp. Added multivoltage, added multicorner and multimode, and implemented several enhancements for the standard IC Compiler Reference Methodology flow. Z-2007.03-SP1 ============= This section describes new features, changes, and enhancements in the IC Compiler Reference Methodology version Z-2007.03-SP1. * Implemented the basic version of the multivoltage flow, which makes use of the Design Compiler multivoltage reference methodologies. Z-2007.03 ========= This section describes new features, changes, and enhancements in the IC Compiler Reference Methodology version Z-2007.03. * Ensures that all designs run fine with this reference methodology use the new release. * Updated for IC Compiler Design Planning Reference Methodology version Z-2007.03, All details are described in the IC Compiler Design Planning Reference Methodology Application Note. * Introduced the new route_opt -initial_route_only command in the route_opt_icc script. * New user interface for multiple CPU contact optimization. Y-2006.06-SP4 ============= This section describes new features, changes, and enhancements in the IC Compiler Reference Methodology version Y-2006.06-SP4. * Update for IC Compiler Design Planning Reference Methodology. All details are described in the IC Compiler Design Planning Reference Methodology Application Note. * New Y-2006.06-SP4 user interface for Delta Max transition during route_opt. * Update on the clock_opt update_io_latency commands. * Better dependency handling in the Makefiles. No longer just a touch of a file, but creating the file from inside IC Compiler, which means that the file will not be created if IC Compiler is unsuccessful. The created file also contains the date info, instead of just an empty file. * Correction for the antenna fixing in the chip finishing section. Y-2006.06-SP3 ============= This section describes new features, changes, and enhancements in the IC Compiler Reference Methodology version Y-2006.06-SP3. * Executes create_qor_snapshot at the end of every script. Depending on the step in the flow, we will generate additional info. For example, after clock_tree, we add clock_tree info, while this is not happening in the create_qor_snapshots before clock tree synthesis. * Removed the CRITICAL_RANGE variable because by default the tool uses 50 percent of the worst negative slack (WNS) per clock domain. This default is recommended. The script contains the correct commands in case you want to change the default behavior. * Executes connect_pg_nets before clock routing to ensure proper connection of tie nets. * Replaced the redirect commands with the redirect operator (>) for improved readability. * Added the new Y-2006.06-SP3 route_opt variables to allow improved max_transition fixing. * Introduced a new icc_setup.tcl variable, ICC_FLOORPLAN_CEL, which is read into the place_opt_icc.tcl script. This variable is used by the IC Compiler Design Planning Reference Methodology, which allows you to create different parallel floorplans. You should select the best floorplan based on congestion and timing analysis values.