### Build the power plan structure
set_fp_rail_constraints -add_layer  -layer METAL3 -direction horizontal -max_strap 4 -min_strap 4 -min_width 0.200 -spacing minimum
set_fp_rail_constraints -add_layer  -layer METAL2 -direction vertical -max_strap 12 -min_strap 2 -min_width 0.200 -spacing minimum
set_fp_rail_constraints  -set_ring -horizontal_ring_layer { METAL5 } -vertical_ring_layer { METAL6 } -ring_max_width 12 -ring_min_width 10 -extend_strap core_ring
set_fp_block_ring_constraints -add -horizontal_layer METAL5 -horizontal_width 3 -horizontal_offset 0.600 -vertical_layer METAL6 -vertical_width 3 -vertical_offset 0.600 -block_type master  -block {  CLKMUL PLL ram16x128 ram32x64 ram4x32 ram8x64} -net  {VDD VSS}
set_fp_rail_constraints -set_global   -no_routing_over_hard_macros
synthesize_fp_rail  -nets {VDD VSS} -voltage_supply 1.32 -synthesize_power_plan -power_budget 760 -pad_masters { pv0i pvdi }
