Initializing gui preferences from file /home/ecelrc/faculty/mark/.synopsys_icc_prefs.tcl icc_shell> gui_start Information: Visibility is turned ON for cells and cell contents because the task is set to Block Implementation (GUI-026) icc_shell> source or1200_alu_route.tcl icc_shell> source route_action.tcl mw_ref_lib is /home/projects/courses/fall_10/ee382m-16947/Artisan/sc/apollo/tsmc18 target_library is typical.db link_library is * typical.db creating milkyway lib Warning: Floating-point attribute 'unitMinCapacitance' is assigned 8.1739e-05 which is too precise and will be truncated to 8.17e-05. (line 88) (TFCHK-035) Warning: Floating-point attribute 'unitNomCapacitance' is assigned 8.1739e-05 which is too precise and will be truncated to 8.17e-05. (line 89) (TFCHK-035) Warning: Floating-point attribute 'unitMaxCapacitance' is assigned 8.1739e-05 which is too precise and will be truncated to 8.17e-05. (line 90) (TFCHK-035) Warning: Floating-point attribute 'unitMinChannelCap' is assigned 3.7826e-05 which is too precise and will be truncated to 3.78e-05. (line 96) (TFCHK-035) Warning: Floating-point attribute 'unitNomChannelCap' is assigned 3.7826e-05 which is too precise and will be truncated to 3.78e-05. (line 97) (TFCHK-035) Warning: Floating-point attribute 'unitMaxChannelCap' is assigned 3.7826e-05 which is too precise and will be truncated to 3.78e-05. (line 98) (TFCHK-035) Warning: Floating-point attribute 'unitMinChannelSideCap' is assigned 1.7280e-05 which is too precise and will be truncated to 1.73e-05. (line 100) (TFCHK-035) Warning: Floating-point attribute 'unitNomChannelSideCap' is assigned 1.7280e-05 which is too precise and will be truncated to 1.73e-05. (line 101) (TFCHK-035) Warning: Floating-point attribute 'unitMaxChannelSideCap' is assigned 1.7280e-05 which is too precise and will be truncated to 1.73e-05. (line 102) (TFCHK-035) Warning: Floating-point attribute 'unitMinCapacitance' is assigned 2.0357e-05 which is too precise and will be truncated to 2.04e-05. (line 138) (TFCHK-035) Warning: Floating-point attribute 'unitNomCapacitance' is assigned 2.0357e-05 which is too precise and will be truncated to 2.04e-05. (line 139) (TFCHK-035) Warning: Floating-point attribute 'unitMaxCapacitance' is assigned 2.0357e-05 which is too precise and will be truncated to 2.04e-05. (line 140) (TFCHK-035) Warning: Floating-point attribute 'unitMinSideWallCap' is assigned 1.2860e-05 which is too precise and will be truncated to 1.29e-05. (line 142) (TFCHK-035) Warning: Floating-point attribute 'unitNomSideWallCap' is assigned 1.2860e-05 which is too precise and will be truncated to 1.29e-05. (line 143) (TFCHK-035) Warning: Floating-point attribute 'unitMaxSideWallCap' is assigned 1.2860e-05 which is too precise and will be truncated to 1.29e-05. (line 144) (TFCHK-035) Warning: Floating-point attribute 'unitMinChannelCap' is assigned 1.5607e-05 which is too precise and will be truncated to 1.56e-05. (line 146) (TFCHK-035) Warning: Floating-point attribute 'unitNomChannelCap' is assigned 1.5607e-05 which is too precise and will be truncated to 1.56e-05. (line 147) (TFCHK-035) Warning: Floating-point attribute 'unitMaxChannelCap' is assigned 1.5607e-05 which is too precise and will be truncated to 1.56e-05. (line 148) (TFCHK-035) Warning: Floating-point attribute 'unitMinChannelSideCap' is assigned 1.1220e-05 which is too precise and will be truncated to 1.12e-05. (line 150) (TFCHK-035) Warning: Floating-point attribute 'unitNomChannelSideCap' is assigned 1.1220e-05 which is too precise and will be truncated to 1.12e-05. (line 151) (TFCHK-035) Warning: Floating-point attribute 'unitMaxChannelSideCap' is assigned 1.1220e-05 which is too precise and will be truncated to 1.12e-05. (line 152) (TFCHK-035) Warning: Floating-point attribute 'unitMinCapacitance' is assigned 1.1393e-05 which is too precise and will be truncated to 1.14e-05. (line 188) (TFCHK-035) Warning: Floating-point attribute 'unitNomCapacitance' is assigned 1.1393e-05 which is too precise and will be truncated to 1.14e-05. (line 189) (TFCHK-035) Warning: Floating-point attribute 'unitMaxCapacitance' is assigned 1.1393e-05 which is too precise and will be truncated to 1.14e-05. (line 190) (TFCHK-035) Warning: Floating-point attribute 'unitMinSideWallCap' is assigned 8.4800e-06 which is too precise and will be truncated to 8.5e-06. (line 192) (TFCHK-035) Warning: Floating-point attribute 'unitNomSideWallCap' is assigned 8.4800e-06 which is too precise and will be truncated to 8.5e-06. (line 193) (TFCHK-035) Warning: Floating-point attribute 'unitMaxSideWallCap' is assigned 8.4800e-06 which is too precise and will be truncated to 8.5e-06. (line 194) (TFCHK-035) Warning: Floating-point attribute 'unitMinChannelCap' is assigned 9.7143e-06 which is too precise and will be truncated to 9.7e-06. (line 196) (TFCHK-035) Warning: Floating-point attribute 'unitNomChannelCap' is assigned 9.7143e-06 which is too precise and will be truncated to 9.7e-06. (line 197) (TFCHK-035) Warning: Floating-point attribute 'unitMaxChannelCap' is assigned 9.7143e-06 which is too precise and will be truncated to 9.7e-06. (line 198) (TFCHK-035) Warning: Floating-point attribute 'unitMinCapacitance' is assigned 7.8929e-06 which is too precise and will be truncated to 7.9e-06. (line 238) (TFCHK-035) Warning: Floating-point attribute 'unitNomCapacitance' is assigned 7.8929e-06 which is too precise and will be truncated to 7.9e-06. (line 239) (TFCHK-035) Warning: Floating-point attribute 'unitMaxCapacitance' is assigned 7.8929e-06 which is too precise and will be truncated to 7.9e-06. (line 240) (TFCHK-035) Warning: Floating-point attribute 'unitMinSideWallCap' is assigned 8.1200e-06 which is too precise and will be truncated to 8.1e-06. (line 242) (TFCHK-035) Warning: Floating-point attribute 'unitNomSideWallCap' is assigned 8.1200e-06 which is too precise and will be truncated to 8.1e-06. (line 243) (TFCHK-035) Warning: Floating-point attribute 'unitMaxSideWallCap' is assigned 8.1200e-06 which is too precise and will be truncated to 8.1e-06. (line 244) (TFCHK-035) Warning: Floating-point attribute 'unitMinChannelCap' is assigned 7.0357e-06 which is too precise and will be truncated to 7e-06. (line 246) (TFCHK-035) Warning: Floating-point attribute 'unitNomChannelCap' is assigned 7.0357e-06 which is too precise and will be truncated to 7e-06. (line 247) (TFCHK-035) Warning: Floating-point attribute 'unitMaxChannelCap' is assigned 7.0357e-06 which is too precise and will be truncated to 7e-06. (line 248) (TFCHK-035) Warning: Floating-point attribute 'unitMinChannelSideCap' is assigned 7.7800e-06 which is too precise and will be truncated to 7.8e-06. (line 250) (TFCHK-035) Warning: Floating-point attribute 'unitNomChannelSideCap' is assigned 7.7800e-06 which is too precise and will be truncated to 7.8e-06. (line 251) (TFCHK-035) Warning: Floating-point attribute 'unitMaxChannelSideCap' is assigned 7.7800e-06 which is too precise and will be truncated to 7.8e-06. (line 252) (TFCHK-035) Warning: Floating-point attribute 'unitMinSideWallCap' is assigned 6.4800e-06 which is too precise and will be truncated to 6.5e-06. (line 292) (TFCHK-035) Warning: Floating-point attribute 'unitNomSideWallCap' is assigned 6.4800e-06 which is too precise and will be truncated to 6.5e-06. (line 293) (TFCHK-035) Warning: Floating-point attribute 'unitMaxSideWallCap' is assigned 6.4800e-06 which is too precise and will be truncated to 6.5e-06. (line 294) (TFCHK-035) Warning: Floating-point attribute 'unitMinChannelSideCap' is assigned 6.2800e-06 which is too precise and will be truncated to 6.3e-06. (line 300) (TFCHK-035) Warning: Floating-point attribute 'unitNomChannelSideCap' is assigned 6.2800e-06 which is too precise and will be truncated to 6.3e-06. (line 301) (TFCHK-035) Warning: Floating-point attribute 'unitMaxChannelSideCap' is assigned 6.2800e-06 which is too precise and will be truncated to 6.3e-06. (line 302) (TFCHK-035) Warning: Floating-point attribute 'unitMinCapacitance' is assigned 4.7500e-06 which is too precise and will be truncated to 4.7e-06. (line 338) (TFCHK-035) Warning: Floating-point attribute 'unitNomCapacitance' is assigned 4.7500e-06 which is too precise and will be truncated to 4.7e-06. (line 339) (TFCHK-035) Warning: Floating-point attribute 'unitMaxCapacitance' is assigned 4.7500e-06 which is too precise and will be truncated to 4.7e-06. (line 340) (TFCHK-035) Warning: Floating-point attribute 'unitMinSideWallCap' is assigned 4.8400e-06 which is too precise and will be truncated to 4.8e-06. (line 342) (TFCHK-035) Warning: Floating-point attribute 'unitNomSideWallCap' is assigned 4.8400e-06 which is too precise and will be truncated to 4.8e-06. (line 343) (TFCHK-035) Warning: Floating-point attribute 'unitMaxSideWallCap' is assigned 4.8400e-06 which is too precise and will be truncated to 4.8e-06. (line 344) (TFCHK-035) Warning: Floating-point attribute 'unitMinChannelCap' is assigned 4.4318e-06 which is too precise and will be truncated to 4.4e-06. (line 346) (TFCHK-035) Warning: Floating-point attribute 'unitNomChannelCap' is assigned 4.4318e-06 which is too precise and will be truncated to 4.4e-06. (line 347) (TFCHK-035) Warning: Floating-point attribute 'unitMaxChannelCap' is assigned 4.4318e-06 which is too precise and will be truncated to 4.4e-06. (line 348) (TFCHK-035) Warning: Floating-point attribute 'minFringeCap' is assigned 8.2045e-05 which is too precise and will be truncated to 8.2e-05. (line 847) (TFCHK-035) Warning: Floating-point attribute 'nomFringeCap' is assigned 8.2045e-05 which is too precise and will be truncated to 8.2e-05. (line 848) (TFCHK-035) Warning: Floating-point attribute 'maxFringeCap' is assigned 8.2045e-05 which is too precise and will be truncated to 8.2e-05. (line 849) (TFCHK-035) Warning: Floating-point attribute 'minFringeCap' is assigned 3.6818e-05 which is too precise and will be truncated to 3.68e-05. (line 857) (TFCHK-035) Warning: Floating-point attribute 'nomFringeCap' is assigned 3.6818e-05 which is too precise and will be truncated to 3.68e-05. (line 858) (TFCHK-035) Warning: Floating-point attribute 'maxFringeCap' is assigned 3.6818e-05 which is too precise and will be truncated to 3.68e-05. (line 859) (TFCHK-035) Warning: Floating-point attribute 'minFringeCap' is assigned 2.5227e-05 which is too precise and will be truncated to 2.52e-05. (line 867) (TFCHK-035) Warning: Floating-point attribute 'nomFringeCap' is assigned 2.5227e-05 which is too precise and will be truncated to 2.52e-05. (line 868) (TFCHK-035) Warning: Floating-point attribute 'maxFringeCap' is assigned 2.5227e-05 which is too precise and will be truncated to 2.52e-05. (line 869) (TFCHK-035) Warning: Floating-point attribute 'minFringeCap' is assigned 2.0205e-05 which is too precise and will be truncated to 2.02e-05. (line 877) (TFCHK-035) Warning: Floating-point attribute 'nomFringeCap' is assigned 2.0205e-05 which is too precise and will be truncated to 2.02e-05. (line 878) (TFCHK-035) Warning: Floating-point attribute 'maxFringeCap' is assigned 2.0205e-05 which is too precise and will be truncated to 2.02e-05. (line 879) (TFCHK-035) Warning: Floating-point attribute 'minFringeCap' is assigned 1.7318e-05 which is too precise and will be truncated to 1.73e-05. (line 887) (TFCHK-035) Warning: Floating-point attribute 'nomFringeCap' is assigned 1.7318e-05 which is too precise and will be truncated to 1.73e-05. (line 888) (TFCHK-035) Warning: Floating-point attribute 'maxFringeCap' is assigned 1.7318e-05 which is too precise and will be truncated to 1.73e-05. (line 889) (TFCHK-035) Warning: Floating-point attribute 'minFringeCap' is assigned 1.0893e-04 which is too precise and will be truncated to 0.0001089. (line 897) (TFCHK-035) Warning: Floating-point attribute 'nomFringeCap' is assigned 1.0893e-04 which is too precise and will be truncated to 0.0001089. (line 898) (TFCHK-035) Warning: Floating-point attribute 'maxFringeCap' is assigned 1.0893e-04 which is too precise and will be truncated to 0.0001089. (line 899) (TFCHK-035) Warning: Floating-point attribute 'minFringeCap' is assigned 5.1429e-05 which is too precise and will be truncated to 5.14e-05. (line 907) (TFCHK-035) Warning: Floating-point attribute 'nomFringeCap' is assigned 5.1429e-05 which is too precise and will be truncated to 5.14e-05. (line 908) (TFCHK-035) Warning: Floating-point attribute 'maxFringeCap' is assigned 5.1429e-05 which is too precise and will be truncated to 5.14e-05. (line 909) (TFCHK-035) Warning: Floating-point attribute 'minFringeCap' is assigned 3.8214e-05 which is too precise and will be truncated to 3.82e-05. (line 917) (TFCHK-035) Warning: Floating-point attribute 'nomFringeCap' is assigned 3.8214e-05 which is too precise and will be truncated to 3.82e-05. (line 918) (TFCHK-035) Warning: Floating-point attribute 'maxFringeCap' is assigned 3.8214e-05 which is too precise and will be truncated to 3.82e-05. (line 919) (TFCHK-035) Warning: Floating-point attribute 'minFringeCap' is assigned 3.1964e-05 which is too precise and will be truncated to 3.2e-05. (line 927) (TFCHK-035) Warning: Floating-point attribute 'nomFringeCap' is assigned 3.1964e-05 which is too precise and will be truncated to 3.2e-05. (line 928) (TFCHK-035) Warning: Floating-point attribute 'maxFringeCap' is assigned 3.1964e-05 which is too precise and will be truncated to 3.2e-05. (line 929) (TFCHK-035) Warning: Floating-point attribute 'minFringeCap' is assigned 1.2429e-04 which is too precise and will be truncated to 0.0001243. (line 937) (TFCHK-035) Warning: Floating-point attribute 'nomFringeCap' is assigned 1.2429e-04 which is too precise and will be truncated to 0.0001243. (line 938) (TFCHK-035) Warning: Floating-point attribute 'maxFringeCap' is assigned 1.2429e-04 which is too precise and will be truncated to 0.0001243. (line 939) (TFCHK-035) Warning: Floating-point attribute 'minFringeCap' is assigned 5.8214e-05 which is too precise and will be truncated to 5.82e-05. (line 947) (TFCHK-035) Warning: Floating-point attribute 'nomFringeCap' is assigned 5.8214e-05 which is too precise and will be truncated to 5.82e-05. (line 948) (TFCHK-035) Warning: Floating-point attribute 'maxFringeCap' is assigned 5.8214e-05 which is too precise and will be truncated to 5.82e-05. (line 949) (TFCHK-035) Warning: Floating-point attribute 'minFringeCap' is assigned 5.2857e-05 which is too precise and will be truncated to 5.29e-05. (line 977) (TFCHK-035) Warning: Floating-point attribute 'nomFringeCap' is assigned 5.2857e-05 which is too precise and will be truncated to 5.29e-05. (line 978) (TFCHK-035) Warning: Floating-point attribute 'maxFringeCap' is assigned 5.2857e-05 which is too precise and will be truncated to 5.29e-05. (line 979) (TFCHK-035) Warning: Floating-point attribute 'minFringeCap' is assigned 1.2536e-04 which is too precise and will be truncated to 0.0001254. (line 987) (TFCHK-035) Warning: Floating-point attribute 'nomFringeCap' is assigned 1.2536e-04 which is too precise and will be truncated to 0.0001254. (line 988) (TFCHK-035) Warning: Floating-point attribute 'maxFringeCap' is assigned 1.2536e-04 which is too precise and will be truncated to 0.0001254. (line 989) (TFCHK-035) Information: Technology attribute 'capacitancePrecision' is assigned 10000000 which causes several capacitance values to be truncated. The recommended capacitance precision is 2147483647. (line 47) (TFCHK-036) Start to load technology file /home/projects/courses/fall_10/ee382m-16947/Artisan/sc/apollo/tf/tsmc18_6lm.tf. Warning: ContactCode 'CONT1' is missing the attribute 'unitMinResistance'. (line 746) (TFCHK-014) Warning: ContactCode 'CONT1' is missing the attribute 'unitNomResistance'. (line 746) (TFCHK-014) Warning: ContactCode 'CONT1' is missing the attribute 'unitMaxResistance'. (line 746) (TFCHK-014) Warning: Cut layer 'VIA12' has a non-cross primary default ContactCode 'via1'. (line 765) (TFCHK-092) Warning: Cut layer 'VIA23' has a non-cross primary default ContactCode 'via2'. (line 784) (TFCHK-092) Warning: Cut layer 'VIA34' has a non-cross primary default ContactCode 'via3'. (line 803) (TFCHK-092) Warning: Cut layer 'VIA45' has a non-cross primary default ContactCode 'via4'. (line 822) (TFCHK-092) Warning: Layer 'METAL1' has a pitch 0.56 that does not match the recommended wire-to-via pitch 0.535 or 0.485. (TFCHK-049) Warning: Layer 'METAL2' has a pitch 0.66 that does not match the recommended wire-to-via pitch 0.61 or 0.56. (TFCHK-049) Warning: Layer 'METAL4' has a pitch 0.66 that does not match the recommended wire-to-via pitch 0.61 or 0.56. (TFCHK-049) Warning: Layer 'METAL3' has a pitch 0.56 that does not match the doubled pitch 1.12 or tripled pitch 1.68. (TFCHK-050) Warning: Layer 'METAL4' has a pitch 0.66 that does not match the doubled pitch 1.32 or tripled pitch 1.98. (TFCHK-050) Warning: Layer 'METAL5' has a pitch 0.61 that does not match the doubled pitch 1.12 or tripled pitch 1.68. (TFCHK-050) Warning: Layer 'METAL6' has a pitch 0.95 that does not match the doubled pitch 1.32 or tripled pitch 1.98. (TFCHK-050) Warning: CapModel sections are missing. Capacitance models should be loaded with a TLU+ file later. (TFCHK-084) Technology file /home/projects/courses/fall_10/ee382m-16947/Artisan/sc/apollo/tf/tsmc18_6lm.tf has been loaded successfully. Sanity check for TLU+ vs MW-Tech files: max_tlu+: /scratch/mark/ICC/starXT_018_6m.tlup min_tlu+: mapping_file: /scratch/mark/ICC/starXT_018_6m.map MW design lib: or1200_alu.mw --------- Sanity Check on TLUPlus Files ------------- 1. Checking the conducting layer names in ITF and mapping file ... [ Passed! ] 2. Checking the via layer names in ITF and mapping file ... [ Passed! ] 3. Checking the consistency of Min Width and Min Spacing between MW-tech and ITF ... [ Passed! ] ----------------- Check Ends ------------------ Loading db file '/home/projects/courses/fall_10/ee382m-16947/Artisan/synopsys/typical.db' Loading db file '/usr/local/packages/synopsys_2010/icc_both/libraries/syn/gtech.db' Loading db file '/usr/local/packages/synopsys_2010/icc_both/libraries/syn/standard.sldb' Type of creating bus for undefined cells : 0 Warning: /home/projects/courses/fall_10/ee382m-16947/Artisan/sc/apollo/tsmc18: bus naming style _<%d> is not consistent with main lib. (MWNL-111) ***** Verilog HDL translation! ***** ***** Start Pass 1 ***** ***** Pass 1 Complete ***** Elapsed = 0:00:00, CPU = 0:00:00 ***** Verilog HDL translation! ***** ***** Start Pass 2 ***** ***** Pass 2 Complete ***** ***** Verilog HDL translation completed! ***** Elapsed = 0:00:00, CPU = 0:00:00 Hierarchy Preservation is turned ON The quick-attach skip-search mode has been turned on. Start axu naming escaping style change ... INFO: net in module or1200_alu renamed from \result_csum[24] to result_csum[24]1 because of name conflict INFO: net in module or1200_alu renamed from \result_sum[24] to result_sum[24]1 because of name conflict INFO: net in module or1200_alu renamed from \result_csum[0] to result_csum[0]1 because of name conflict INFO: net in module or1200_alu renamed from \result_sum[0] to result_sum[0]1 because of name conflict INFO: net in module or1200_alu renamed from \result_csum[13] to result_csum[13]1 because of name conflict INFO: net in module or1200_alu renamed from \result_sum[13] to result_sum[13]1 because of name conflict INFO: net in module or1200_alu renamed from \result_csum[22] to result_csum[22]1 because of name conflict INFO: net in module or1200_alu renamed from \result_sum[22] to result_sum[22]1 because of name conflict INFO: net in module or1200_alu renamed from \result_csum[31] to result_csum[31]1 because of name conflict INFO: net in module or1200_alu renamed from \result_sum[31] to result_sum[31]1 because of name conflict INFO: net in module or1200_alu renamed from \result_csum[5] to result_csum[5]1 because of name conflict INFO: net in module or1200_alu renamed from \result_sum[5] to result_sum[5]1 because of name conflict INFO: net in module or1200_alu renamed from \result_csum[30] to result_csum[30]1 because of name conflict INFO: net in module or1200_alu renamed from \result_sum[30] to result_sum[30]1 because of name conflict INFO: net in module or1200_alu renamed from \result_csum[23] to result_csum[23]1 because of name conflict INFO: net in module or1200_alu renamed from \result_sum[23] to result_sum[23]1 because of name conflict INFO: net in module or1200_alu renamed from \result_csum[25] to result_csum[25]1 because of name conflict INFO: net in module or1200_alu renamed from \result_sum[25] to result_sum[25]1 because of name conflict INFO: net in module or1200_alu renamed from \result_csum[3] to result_csum[3]1 because of name conflict INFO: net in module or1200_alu renamed from \result_sum[3] to result_sum[3]1 because of name conflict INFO: net in module or1200_alu renamed from \result_csum[4] to result_csum[4]1 because of name conflict INFO: net in module or1200_alu renamed from \result_sum[4] to result_sum[4]1 because of name conflict INFO: net in module or1200_alu renamed from \result_csum[27] to result_csum[27]1 because of name conflict INFO: net in module or1200_alu renamed from \result_sum[27] to result_sum[27]1 because of name conflict INFO: net in module or1200_alu renamed from \result_csum[19] to result_csum[19]1 because of name conflict INFO: net in module or1200_alu renamed from \result_sum[19] to result_sum[19]1 because of name conflict INFO: net in module or1200_alu renamed from \result_csum[16] to result_csum[16]1 because of name conflict INFO: net in module or1200_alu renamed from \result_sum[16] to result_sum[16]1 because of name conflict INFO: net in module or1200_alu renamed from \result_sum[20] to result_sum[20]1 because of name conflict INFO: net in module or1200_alu renamed from \result_sum[26] to result_sum[26]1 because of name conflict INFO: net in module or1200_alu renamed from \result_csum[17] to result_csum[17]1 because of name conflict INFO: net in module or1200_alu renamed from \result_sum[17] to result_sum[17]1 because of name conflict INFO: net in module or1200_alu renamed from \result_csum[9] to result_csum[9]1 because of name conflict INFO: net in module or1200_alu renamed from \result_sum[9] to result_sum[9]1 because of name conflict INFO: net in module or1200_alu renamed from \result_csum[28] to result_csum[28]1 because of name conflict INFO: net in module or1200_alu renamed from \result_sum[28] to result_sum[28]1 because of name conflict INFO: net in module or1200_alu renamed from \result_csum[10] to result_csum[10]1 because of name conflict INFO: net in module or1200_alu renamed from \result_sum[10] to result_sum[10]1 because of name conflict INFO: net in module or1200_alu renamed from \result_sum[21] to result_sum[21]1 because of name conflict INFO: net in module or1200_alu renamed from \result_csum[14] to result_csum[14]1 because of name conflict INFO: net in module or1200_alu renamed from \result_sum[14] to result_sum[14]1 because of name conflict INFO: net in module or1200_alu renamed from \result_csum[12] to result_csum[12]1 because of name conflict INFO: net in module or1200_alu renamed from \result_sum[12] to result_sum[12]1 because of name conflict INFO: net in module or1200_alu renamed from \result_csum[11] to result_csum[11]1 because of name conflict INFO: net in module or1200_alu renamed from \result_sum[11] to result_sum[11]1 because of name conflict INFO: net in module or1200_alu renamed from \result_csum[29] to result_csum[29]1 because of name conflict INFO: net in module or1200_alu renamed from \result_sum[29] to result_sum[29]1 because of name conflict INFO: net in module or1200_alu renamed from \result_csum[8] to result_csum[8]1 because of name conflict INFO: net in module or1200_alu renamed from \result_sum[8] to result_sum[8]1 because of name conflict INFO: net in module or1200_alu renamed from \result_csum[15] to result_csum[15]1 because of name conflict INFO: net in module or1200_alu renamed from \result_sum[15] to result_sum[15]1 because of name conflict INFO: net in module or1200_alu renamed from \result_csum[2] to result_csum[2]1 because of name conflict INFO: net in module or1200_alu renamed from \result_sum[2] to result_sum[2]1 because of name conflict End axu naming escaping style change, status is 1 Checking single pin net for cell 'or1200_alu.CEL' now... Total number of cell instances: 2733 Total number of nets: 2853 Total number of ports: 156 (include 0 PG ports) Total number of hierarchical cell instances: 1 The quick-attach skip-search mode has been turned off. INFO: total find 0 pg nets connected with tie net. Elapsed = 0:00:01, CPU = 0:00:00 Information: Read verilog completed successfully. Warning: No designs to list. (UID-275) Information: linking reference library : /home/projects/courses/fall_10/ee382m-16947/Artisan/sc/apollo/tsmc18. (PSYN-878) Linking design 'or1200_alu' Using the following designs and libraries: -------------------------------------------------------------------------- or1200_alu or1200_alu.CEL typical (library) /home/projects/courses/fall_10/ee382m-16947/Artisan/synopsys/typical.db Load global CTS reference options from NID to stack Warning: No uniquify allowed on design with Milkyway already written in IC Compiler. (MWDC-030) Linking design 'or1200_alu' Using the following designs and libraries: -------------------------------------------------------------------------- or1200_alu or1200_alu.CEL typical (library) /home/projects/courses/fall_10/ee382m-16947/Artisan/synopsys/typical.db Info: Writing NID in 3.0 format Info: Writing NID in 3.0 format There are 156 pins in total Core aspect ratio adjusted to 1.487 Core Utilization adjusted to 0.836 Start to create wire tracks ... GRC reference (-4040,-4040), dimensions (5040, 5040) Warning: Pin constraints not found for top block. Default pin constraints are saved. (FPHSM-0010) Warning: Cell instance add_x_187_0\/U303 is not completely placed inside top block or1200_alu (FPHSM-1800) Warning: Current cell: cell placement is incomplete and will be ignored (FPHSM-1829) Number of terminals created: 156. =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- Name Original Ports or1200_alu 156 =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- Completed pin assignment. Elapsed = 0:00:00, CPU = 0:00:00 Planner Summary: This floorplan is created by using tile name (unit). Row Direction = HORIZONTAL Control Parameter = Width & Height Core Utilization = 0.836 Number Of Rows = 59 Core Width = 199.98 Core Height = 297.36 Aspect Ratio = 1.487 Double Back ON Flip First Row = NO Start From First Row = NO Planner run through successfully. next: update_pg begin derive_pg_connection... --- connected 2733 power ports and 2733 ground ports next: read_pin_pad_physical_constraints 156 pins are constrained in TDF table There are 156 pins in total Core aspect ratio adjusted to 1.487 Core Utilization adjusted to 0.836 Start to create wire tracks ... GRC reference (-4040,-4040), dimensions (5040, 5040) Warning: Cell instance add_x_187_0\/U303 is not completely placed inside top block or1200_alu (FPHSM-1800) Warning: Current cell: cell placement is incomplete and will be ignored (FPHSM-1829) Number of terminals created: 156. =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- Name Original Ports or1200_alu 156 =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- Completed pin assignment. Elapsed = 0:00:00, CPU = 0:00:00 Planner Summary: This floorplan is created by using tile name (unit). Row Direction = HORIZONTAL Control Parameter = Width & Height Core Utilization = 0.836 Number Of Rows = 59 Core Width = 199.98 Core Height = 297.36 Aspect Ratio = 1.487 Double Back ON Flip First Row = NO Start From First Row = NO Planner run through successfully. next: update_pg begin derive_pg_connection... --- connected 2733 power ports and 2733 ground ports next: set fixed placement objects Information: linking reference library : /home/projects/courses/fall_10/ee382m-16947/Artisan/sc/apollo/tsmc18. (PSYN-878) Linking design 'or1200_alu' Using the following designs and libraries: -------------------------------------------------------------------------- or1200_alu or1200_alu.CEL typical (library) /home/projects/courses/fall_10/ee382m-16947/Artisan/synopsys/typical.db Load global CTS reference options from NID to stack Information: Performing CEL netlist consistency check. (MWDC-118) Information: CEL consistency check PASSED. (MWDC-119) Information: The design has horizontal rows, and Y-symmetry has been used for sites. (MWDC-217) Floorplan loading succeeded. Info: Writing NID in 3.0 format Info: Writing NID in 3.0 format Information: Saved design named or1200_alu_macros_placed. (UIG-5) NOTE: Creating power straps 2733 cells out of bound WARNING: potential strap segment out of bounds and ignored ((1.000, 333.190) (200.980, 334.090)) (Net: VSS)(wire on layer: METAL3 [28]) WARNING: potential strap segment out of bounds and ignored ((1.000, 373.510) (200.980, 374.410)) (Net: VSS)(wire on layer: METAL3 [28]) WARNING: potential strap segment out of bounds and ignored ((1.000, 413.830) (200.980, 414.730)) (Net: VSS)(wire on layer: METAL3 [28]) WARNING: potential strap segment out of bounds and ignored ((1.000, 454.150) (200.980, 455.050)) (Net: VSS)(wire on layer: METAL3 [28]) WARNING: potential strap segment out of bounds and ignored ((1.000, 494.470) (200.980, 495.370)) (Net: VSS)(wire on layer: METAL3 [28]) WARNING: potential strap segment out of bounds and ignored ((1.000, 534.790) (200.980, 535.690)) (Net: VSS)(wire on layer: METAL3 [28]) WARNING: potential strap segment out of bounds and ignored ((1.000, 575.110) (200.980, 576.010)) (Net: VSS)(wire on layer: METAL3 [28]) WARNING: potential strap segment out of bounds and ignored ((1.000, 615.430) (200.980, 616.330)) (Net: VSS)(wire on layer: METAL3 [28]) WARNING: potential strap segment out of bounds and ignored ((1.000, 655.750) (200.980, 656.650)) (Net: VSS)(wire on layer: METAL3 [28]) WARNING: potential strap segment out of bounds and ignored ((1.000, 696.070) (200.980, 696.970)) (Net: VSS)(wire on layer: METAL3 [28]) WARNING: potential strap segment out of bounds and ignored ((1.000, 736.390) (200.980, 737.290)) (Net: VSS)(wire on layer: METAL3 [28]) WARNING: potential strap segment out of bounds and ignored ((1.000, 776.710) (200.980, 777.610)) (Net: VSS)(wire on layer: METAL3 [28]) [Prerouter] CPU = 0:00:00, Elapsed = 0:00:00 Peak Memory = 118M Data = 0M WARNING: potential strap segment out of bounds and ignored ((1.000, 328.150) (200.980, 329.050)) (Net: VDD)(wire on layer: METAL3 [28]) WARNING: potential strap segment out of bounds and ignored ((1.000, 368.470) (200.980, 369.370)) (Net: VDD)(wire on layer: METAL3 [28]) WARNING: potential strap segment out of bounds and ignored ((1.000, 408.790) (200.980, 409.690)) (Net: VDD)(wire on layer: METAL3 [28]) WARNING: potential strap segment out of bounds and ignored ((1.000, 449.110) (200.980, 450.010)) (Net: VDD)(wire on layer: METAL3 [28]) WARNING: potential strap segment out of bounds and ignored ((1.000, 489.430) (200.980, 490.330)) (Net: VDD)(wire on layer: METAL3 [28]) WARNING: potential strap segment out of bounds and ignored ((1.000, 529.750) (200.980, 530.650)) (Net: VDD)(wire on layer: METAL3 [28]) WARNING: potential strap segment out of bounds and ignored ((1.000, 570.070) (200.980, 570.970)) (Net: VDD)(wire on layer: METAL3 [28]) WARNING: potential strap segment out of bounds and ignored ((1.000, 610.390) (200.980, 611.290)) (Net: VDD)(wire on layer: METAL3 [28]) WARNING: potential strap segment out of bounds and ignored ((1.000, 650.710) (200.980, 651.610)) (Net: VDD)(wire on layer: METAL3 [28]) WARNING: potential strap segment out of bounds and ignored ((1.000, 691.030) (200.980, 691.930)) (Net: VDD)(wire on layer: METAL3 [28]) WARNING: potential strap segment out of bounds and ignored ((1.000, 731.350) (200.980, 732.250)) (Net: VDD)(wire on layer: METAL3 [28]) WARNING: potential strap segment out of bounds and ignored ((1.000, 771.670) (200.980, 772.570)) (Net: VDD)(wire on layer: METAL3 [28]) [Prerouter] CPU = 0:00:00, Elapsed = 0:00:00 Peak Memory = 118M Data = 0M WARNING: potential strap segment out of bounds and ignored ((211.230, 1.000) (212.130, 298.360)) (Net: VSS)(wire on layer: METAL4 [31]) WARNING: potential strap segment out of bounds and ignored ((251.550, 1.000) (252.450, 298.360)) (Net: VSS)(wire on layer: METAL4 [31]) WARNING: potential strap segment out of bounds and ignored ((291.870, 1.000) (292.770, 298.360)) (Net: VSS)(wire on layer: METAL4 [31]) WARNING: potential strap segment out of bounds and ignored ((332.190, 1.000) (333.090, 298.360)) (Net: VSS)(wire on layer: METAL4 [31]) WARNING: potential strap segment out of bounds and ignored ((372.510, 1.000) (373.410, 298.360)) (Net: VSS)(wire on layer: METAL4 [31]) WARNING: potential strap segment out of bounds and ignored ((412.830, 1.000) (413.730, 298.360)) (Net: VSS)(wire on layer: METAL4 [31]) WARNING: potential strap segment out of bounds and ignored ((453.150, 1.000) (454.050, 298.360)) (Net: VSS)(wire on layer: METAL4 [31]) WARNING: potential strap segment out of bounds and ignored ((493.470, 1.000) (494.370, 298.360)) (Net: VSS)(wire on layer: METAL4 [31]) WARNING: potential strap segment out of bounds and ignored ((533.790, 1.000) (534.690, 298.360)) (Net: VSS)(wire on layer: METAL4 [31]) WARNING: potential strap segment out of bounds and ignored ((574.110, 1.000) (575.010, 298.360)) (Net: VSS)(wire on layer: METAL4 [31]) WARNING: potential strap segment out of bounds and ignored ((614.430, 1.000) (615.330, 298.360)) (Net: VSS)(wire on layer: METAL4 [31]) WARNING: potential strap segment out of bounds and ignored ((654.750, 1.000) (655.650, 298.360)) (Net: VSS)(wire on layer: METAL4 [31]) WARNING: potential strap segment out of bounds and ignored ((695.070, 1.000) (695.970, 298.360)) (Net: VSS)(wire on layer: METAL4 [31]) WARNING: potential strap segment out of bounds and ignored ((735.390, 1.000) (736.290, 298.360)) (Net: VSS)(wire on layer: METAL4 [31]) WARNING: potential strap segment out of bounds and ignored ((775.710, 1.000) (776.610, 298.360)) (Net: VSS)(wire on layer: METAL4 [31]) [Prerouter] CPU = 0:00:00, Elapsed = 0:00:00 Peak Memory = 118M Data = 0M WARNING: potential strap segment out of bounds and ignored ((206.190, 1.000) (207.090, 298.360)) (Net: VDD)(wire on layer: METAL4 [31]) WARNING: potential strap segment out of bounds and ignored ((246.510, 1.000) (247.410, 298.360)) (Net: VDD)(wire on layer: METAL4 [31]) WARNING: potential strap segment out of bounds and ignored ((286.830, 1.000) (287.730, 298.360)) (Net: VDD)(wire on layer: METAL4 [31]) WARNING: potential strap segment out of bounds and ignored ((327.150, 1.000) (328.050, 298.360)) (Net: VDD)(wire on layer: METAL4 [31]) WARNING: potential strap segment out of bounds and ignored ((367.470, 1.000) (368.370, 298.360)) (Net: VDD)(wire on layer: METAL4 [31]) WARNING: potential strap segment out of bounds and ignored ((407.790, 1.000) (408.690, 298.360)) (Net: VDD)(wire on layer: METAL4 [31]) WARNING: potential strap segment out of bounds and ignored ((448.110, 1.000) (449.010, 298.360)) (Net: VDD)(wire on layer: METAL4 [31]) WARNING: potential strap segment out of bounds and ignored ((488.430, 1.000) (489.330, 298.360)) (Net: VDD)(wire on layer: METAL4 [31]) WARNING: potential strap segment out of bounds and ignored ((528.750, 1.000) (529.650, 298.360)) (Net: VDD)(wire on layer: METAL4 [31]) WARNING: potential strap segment out of bounds and ignored ((569.070, 1.000) (569.970, 298.360)) (Net: VDD)(wire on layer: METAL4 [31]) WARNING: potential strap segment out of bounds and ignored ((609.390, 1.000) (610.290, 298.360)) (Net: VDD)(wire on layer: METAL4 [31]) WARNING: potential strap segment out of bounds and ignored ((649.710, 1.000) (650.610, 298.360)) (Net: VDD)(wire on layer: METAL4 [31]) WARNING: potential strap segment out of bounds and ignored ((690.030, 1.000) (690.930, 298.360)) (Net: VDD)(wire on layer: METAL4 [31]) WARNING: potential strap segment out of bounds and ignored ((730.350, 1.000) (731.250, 298.360)) (Net: VDD)(wire on layer: METAL4 [31]) WARNING: potential strap segment out of bounds and ignored ((770.670, 1.000) (771.570, 298.360)) (Net: VDD)(wire on layer: METAL4 [31]) [Prerouter] CPU = 0:00:00, Elapsed = 0:00:00 Peak Memory = 119M Data = 0M Information: Performing CEL netlist consistency check. (MWDC-118) Information: CEL consistency check PASSED. (MWDC-119) Info: Writing NID in 3.0 format Info: Writing NID in 3.0 format Information: Saved design named or1200_alu_power_strap. (UIG-5) Loading design 'or1200_alu' Information: Library Manufacturing Grid(GridResolution) : 5 Information: Time Unit from Milkyway design library: 'ns' Information: Design Library and main library timing units are matched - 1.000 ns. Information: Resistance Unit from Milkyway design library: 'kohm' Information: Design Library and main library resistance units are matched - 1.000 kohm. Information: Capacitance Unit from Milkyway design library: 'pf' Information: Design Library and main library capacitance units are matched - 1.000 pf. Information: Layer METAL1 is ignored for resistance and capacitance computation. (RCEX-019) Information: Layer METAL5 is ignored for resistance and capacitance computation. (RCEX-019) Information: Layer METAL6 is ignored for resistance and capacitance computation. (RCEX-019) TLU+ File = /scratch/mark/ICC/starXT_018_6m.tlup --------- Sanity Check on TLUPlus Files ------------- 1. Checking the conducting layer names in ITF and mapping file ... [ Passed! ] 2. Checking the via layer names in ITF and mapping file ... [ Passed! ] 3. Checking the consistency of Min Width and Min Spacing between MW-tech and ITF ... [ Passed! ] ----------------- Check Ends ------------------ **************************************************************** Information: TLUPlus based RC computation is enabled. (RCEX-141) **************************************************************** Information: The distance unit in Capacitance and Resistance is 1 micron. (RCEX-007) Information: The RC model used is TLU+. (RCEX-015) Information: Library Derived Cap for layer METAL1 : 0.00021 0.00021 (RCEX-011) Information: Library Derived Res for layer METAL1 : 0.00044 0.00044 (RCEX-011) Information: Library Derived Cap for layer METAL2 : 0.0002 0.0002 (RCEX-011) Information: Library Derived Res for layer METAL2 : 0.00036 0.00036 (RCEX-011) Information: Library Derived Cap for layer METAL3 : 0.00024 0.00024 (RCEX-011) Information: Library Derived Res for layer METAL3 : 0.00036 0.00036 (RCEX-011) Information: Library Derived Cap for layer METAL4 : 0.0002 0.0002 (RCEX-011) Information: Library Derived Res for layer METAL4 : 0.00036 0.00036 (RCEX-011) Information: Library Derived Cap for layer METAL5 : 0.00021 0.00021 (RCEX-011) Information: Library Derived Res for layer METAL5 : 0.00036 0.00036 (RCEX-011) Information: Library Derived Cap for layer METAL6 : 0.00027 0.00027 (RCEX-011) Information: Library Derived Res for layer METAL6 : 0.0001 0.0001 (RCEX-011) Information: Library Derived Horizontal Cap : 0.00024 0.00024 (RCEX-011) Information: Library Derived Horizontal Res : 0.00036 0.00036 (RCEX-011) Information: Library Derived Vertical Cap : 0.0002 0.0002 (RCEX-011) Information: Library Derived Vertical Res : 0.00036 0.00036 (RCEX-011) Information: Using derived R and C coefficients. (RCEX-008) Information: Using region-based R and C coefficients. (RCEX-013) Information: Library Derived Via Res : 0.0064 0.0064 (RCEX-011) Beginning Coarse Placement -------------------------- Information: Running stand-alone coarse placer in a separate process using temp directory '/tmp'. (PSYN-605) ...25%...50%...75%...100% done. Coarse Placement Complete -------------------------- Information: Updating database... Loading design 'or1200_alu' Information: Library Manufacturing Grid(GridResolution) : 5 Information: Time Unit from Milkyway design library: 'ns' Information: Design Library and main library timing units are matched - 1.000 ns. Information: Resistance Unit from Milkyway design library: 'kohm' Information: Design Library and main library resistance units are matched - 1.000 kohm. Information: Capacitance Unit from Milkyway design library: 'pf' Information: Design Library and main library capacitance units are matched - 1.000 pf. Information: Layer METAL1 is ignored for resistance and capacitance computation. (RCEX-019) Information: Layer METAL5 is ignored for resistance and capacitance computation. (RCEX-019) Information: Layer METAL6 is ignored for resistance and capacitance computation. (RCEX-019) **************************************************************** Information: TLUPlus based RC computation is enabled. (RCEX-141) **************************************************************** Information: The distance unit in Capacitance and Resistance is 1 micron. (RCEX-007) Information: The RC model used is TLU+. (RCEX-015) Information: Library Derived Cap for layer METAL1 : 0.00021 0.00021 (RCEX-011) Information: Library Derived Res for layer METAL1 : 0.00044 0.00044 (RCEX-011) Information: Library Derived Cap for layer METAL2 : 0.0002 0.0002 (RCEX-011) Information: Library Derived Res for layer METAL2 : 0.00036 0.00036 (RCEX-011) Information: Library Derived Cap for layer METAL3 : 0.00024 0.00024 (RCEX-011) Information: Library Derived Res for layer METAL3 : 0.00036 0.00036 (RCEX-011) Information: Library Derived Cap for layer METAL4 : 0.0002 0.0002 (RCEX-011) Information: Library Derived Res for layer METAL4 : 0.00036 0.00036 (RCEX-011) Information: Library Derived Cap for layer METAL5 : 0.00021 0.00021 (RCEX-011) Information: Library Derived Res for layer METAL5 : 0.00036 0.00036 (RCEX-011) Information: Library Derived Cap for layer METAL6 : 0.00027 0.00027 (RCEX-011) Information: Library Derived Res for layer METAL6 : 0.0001 0.0001 (RCEX-011) Information: Library Derived Horizontal Cap : 0.00024 0.00024 (RCEX-011) Information: Library Derived Horizontal Res : 0.00036 0.00036 (RCEX-011) Information: Library Derived Vertical Cap : 0.0002 0.0002 (RCEX-011) Information: Library Derived Vertical Res : 0.00036 0.00036 (RCEX-011) Information: Using derived R and C coefficients. (RCEX-008) Information: Using region-based R and C coefficients. (RCEX-013) Information: Library Derived Via Res : 0.0064 0.0064 (RCEX-011) Legalizing Placement -------------------- [begin initializing data for legality checker] Initializing Data Structure ... Reading technology information ... Technology table contains 6 routable metal layers Top most routable layer is set to be metal4 This is considered as a 4-metal-layer design Reading library information from DB ... Reading misc information ... array has 0 vertical and 59 horizontal rows GRC ref loc X corrected GRC ref loc Y corrected 26 pre-routes for placement blockage/checking 106 pre-routes for map congestion calculation Checking information read in ... design style = Horizontal masters, Horizontal rows Preprocessing design ... splitting rows by natural obstacles ... [end initializing data for legality checker] **************************************** Report : Chip Summary Design : or1200_alu Version: D-2010.03-ICC-SP1 Date : Tue Nov 2 10:26:06 2010 **************************************** Std cell utilization: 83.56% (14938/(17877-0)) (Non-fixed + Fixed) Std cell utilization: 83.56% (14938/(17877-0)) (Non-fixed only) Chip area: 17877 sites, bbox (1.00 1.00 200.98 298.36) um Std cell area: 14938 sites, (non-fixed:14938 fixed:0) 2733 cells, (non-fixed:2733 fixed:0) Macro cell area: 0 sites 0 cells Placement blockages: 0 sites, (excluding fixed std cells) 0 sites, (include fixed std cells & chimney area) 0 sites, (complete p/g net blockages) Routing blockages: 0 sites, (partial p/g net blockages) 0 sites, (routing blockages and signal pre-route) Lib cell count: 109 Avg. std cell width: 4.89 um Site array: unit (width: 0.66 um, height: 5.04 um, rows: 59) Physical DB scale: 1000 db_unit = 1 um **************************************** Report : pnet options Design : or1200_alu Version: D-2010.03-ICC-SP1 Date : Tue Nov 2 10:26:06 2010 **************************************** -------------------------------------------------------------------- Layer Blockage Min_width Min_height Via_additive Density -------------------------------------------------------------------- METAL1 none --- --- via additive --- METAL2 none --- --- via additive --- METAL3 none --- --- via additive --- METAL4 none --- --- via additive --- METAL5 none --- --- via additive --- METAL6 none --- --- via additive --- Legalizing 2733 illegal cells... Starting legalizer. Initial legalization: 100% (0 sec) Optimizations pass 1: 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% (0 sec) Optimizations pass 2: 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% (0 sec) Optimizations pass 3: 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% (0 sec) Legalization complete (1 total sec) **************************************** Report : Legalize Displacement Design : or1200_alu Version: D-2010.03-ICC-SP1 Date : Tue Nov 2 10:26:06 2010 **************************************** avg cell displacement: 1.470 um ( 0.29 row height) max cell displacement: 5.044 um ( 1.00 row height) std deviation: 0.779 um ( 0.15 row height) number of cell moved: 2733 cells (out of 2733 cells) Total 0 cells has large displacement (e.g. > 15.120 um or 3 row height) Placement Legalization Complete ------------------------------- [begin initializing data for legality checker] Initializing Data Structure ... Reading technology information ... Technology table contains 6 routable metal layers Top most routable layer is set to be metal4 This is considered as a 4-metal-layer design Reading library information from DB ... Reading misc information ... array has 0 vertical and 59 horizontal rows GRC ref loc X corrected GRC ref loc Y corrected 26 pre-routes for placement blockage/checking 106 pre-routes for map congestion calculation Checking information read in ... design style = Horizontal masters, Horizontal rows Preprocessing design ... splitting rows by natural obstacles ... [end initializing data for legality checker] Warning: Die area is not integer multiples of min site height (5040), object's width and height(201980,299360). (PSYN-523) Warning: Die area is not integer multiples of min site width (660), object's width and height(201980,299360). (PSYN-523) **************************************************** Check_legality: Report for Fixed Placement Cells Information: Use the -verbose option to get details about the legality violations. (PSYN-054) **************************************************** (fixed placement) Cells Not on Row : 0 (fixed placement) Cell Overlaps : 0 (fixed placement) Cells overlapping blockages : 0 (fixed placement) Orientation Violations : 0 (fixed placement) Site Violations : 0 (fixed placement) Power Strap Violations : 0 ****************************************************** ****************************************************** Check_legality: Report for Non-fixed Placement Cells Information: Use the -verbose option to get details about the legality violations. (PSYN-054) ****************************************************** Number of Cells Not on Row : 0 Number of Cell Overlaps : 0 Number of Cells overlapping blockages : 0 Number of Orientation Violations : 0 Number of Site Violations : 0 Number of Power Strap Violations : 0 ******************************************** Information: Updating database... Information: Performing CEL netlist consistency check. (MWDC-118) Information: CEL consistency check PASSED. (MWDC-119) Info: Writing NID in 3.0 format Info: Writing NID in 3.0 format Information: Saved design named or1200_alu_legalize_placement. (UIG-5) The options for place_opt: -------------------------- POPT: place_opt effort level : medium POPT: Congestion removal : Yes POPT: Area recovery : No POPT: Optimize dft : No POPT: Clock Tree Synthesis : No POPT: Optimize power : No --------------------------------------------------- Settings of some common used Tcl variables for place_opt: --------------------------------------------------------- placer_run_in_separate_process : TRUE --------------------------------------------------------- Loading design 'or1200_alu' Information: Library Manufacturing Grid(GridResolution) : 5 Information: Time Unit from Milkyway design library: 'ns' Information: Design Library and main library timing units are matched - 1.000 ns. Information: Resistance Unit from Milkyway design library: 'kohm' Information: Design Library and main library resistance units are matched - 1.000 kohm. Information: Capacitance Unit from Milkyway design library: 'pf' Information: Design Library and main library capacitance units are matched - 1.000 pf. Information: Layer METAL1 is ignored for resistance and capacitance computation. (RCEX-019) Information: Layer METAL5 is ignored for resistance and capacitance computation. (RCEX-019) Information: Layer METAL6 is ignored for resistance and capacitance computation. (RCEX-019) **************************************************************** Information: TLUPlus based RC computation is enabled. (RCEX-141) **************************************************************** Information: The distance unit in Capacitance and Resistance is 1 micron. (RCEX-007) Information: The RC model used is TLU+. (RCEX-015) Information: Library Derived Cap for layer METAL1 : 0.00021 0.00021 (RCEX-011) Information: Library Derived Res for layer METAL1 : 0.00044 0.00044 (RCEX-011) Information: Library Derived Cap for layer METAL2 : 0.0002 0.0002 (RCEX-011) Information: Library Derived Res for layer METAL2 : 0.00036 0.00036 (RCEX-011) Information: Library Derived Cap for layer METAL3 : 0.00024 0.00024 (RCEX-011) Information: Library Derived Res for layer METAL3 : 0.00036 0.00036 (RCEX-011) Information: Library Derived Cap for layer METAL4 : 0.0002 0.0002 (RCEX-011) Information: Library Derived Res for layer METAL4 : 0.00036 0.00036 (RCEX-011) Information: Library Derived Cap for layer METAL5 : 0.00021 0.00021 (RCEX-011) Information: Library Derived Res for layer METAL5 : 0.00036 0.00036 (RCEX-011) Information: Library Derived Cap for layer METAL6 : 0.00027 0.00027 (RCEX-011) Information: Library Derived Res for layer METAL6 : 0.0001 0.0001 (RCEX-011) Information: Library Derived Horizontal Cap : 0.00024 0.00024 (RCEX-011) Information: Library Derived Horizontal Res : 0.00036 0.00036 (RCEX-011) Information: Library Derived Vertical Cap : 0.0002 0.0002 (RCEX-011) Information: Library Derived Vertical Res : 0.00036 0.00036 (RCEX-011) Information: Using derived R and C coefficients. (RCEX-008) Information: Using region-based R and C coefficients. (RCEX-013) Information: Library Derived Via Res : 0.0064 0.0064 (RCEX-011) Beginning Coarse Placement -------------------------- Information: Running stand-alone coarse placer in a separate process using temp directory '/tmp'. (PSYN-605) ...25%...50%...75%...100% done. Coarse Placement Complete -------------------------- High fanout optimization starts ================================================================ Information: Total number of removal drivers is 6. (HFS-800) Information: Automatic high-fanout synthesis in progress for high fanout nets. (PSYN-869) Information: Total number of insertion drivers is 6. (HFS-801) Information: Automatic high-fanout synthesis deletes 93 cells. (HFS-802) Information: Automatic high-fanout synthesis adds 30 new cells. (PSYN-864) ELAPSED WORST NEG TOTAL NEG DESIGN TIME AREA SLACK SLACK RULE COST ENDPOINT --------- --------- --------- --------- --------- ------------------------- 0:00:05 49809.5 0.62 408.3 0.0 0:00:05 49809.5 0.62 408.3 0.0 Optimization Complete --------------------- High fanout optimization completes ================================================================ WNS: 0.63 TNS: 16.58 Number of Violating Paths: 36 Nets with DRC Violations: 0 Total moveable cell area: 49809.7 Total fixed cell area: 0.0 Core area: (1000 1000 200980 298360) Timing and DRC Optimization (Stage 1) -------------------------------------- Beginning Timing Optimizations ------------------------------ ELAPSED WORST NEG TOTAL NEG DESIGN TIME AREA SLACK SLACK RULE COST ENDPOINT --------- --------- --------- --------- --------- ------------------------- 0:00:07 49809.5 0.63 421.2 0.0 Optimization Complete --------------------- Beginning Timing Optimizations ------------------------------ ELAPSED WORST NEG TOTAL NEG DESIGN TIME AREA SLACK SLACK RULE COST ENDPOINT --------- --------- --------- --------- --------- ------------------------- 0:00:07 49809.5 0.63 421.2 0.0 0:00:09 50311.8 0.50 400.6 0.0 result[5] 0:00:11 50338.4 0.48 382.8 0.0 result[17] 0:00:13 50488.1 0.46 358.4 0.0 result[2] 0:00:15 50577.9 0.42 326.3 0.0 cyforw 0:00:17 50667.7 0.38 310.5 0.0 result[16] 0:00:20 50697.7 0.35 277.5 0.0 result[2] 0:00:22 51143.4 0.33 261.8 0.0 result[2] 0:00:24 51386.2 0.30 250.9 0.0 result[3] 0:00:26 51665.6 0.29 248.7 0.0 result[10] 0:00:28 51871.9 0.28 229.2 0.0 result[20] 0:00:30 52144.6 0.27 215.8 0.0 result[21] 0:00:32 52051.5 0.27 206.9 0.0 result[3] 0:00:33 52191.2 0.26 207.2 0.0 result[30] 0:00:34 52307.6 0.26 208.7 0.0 result[12] 0:00:35 52387.5 0.26 199.0 0.0 result[5] 0:00:36 52407.4 0.25 196.2 0.0 result[14] 0:00:37 52540.5 0.25 195.2 0.0 result[0] 0:00:38 52630.3 0.25 194.7 0.0 result[18] 0:00:38 52783.3 0.25 191.6 0.0 flag_we 0:00:39 52923.0 0.25 187.7 0.0 result[30] 0:00:41 52986.2 0.24 185.8 0.0 result[29] 0:00:41 52996.2 0.24 186.7 0.0 result[2] 0:00:42 53069.4 0.24 185.7 0.0 result[5] 0:00:43 53109.3 0.24 184.9 0.0 result[5] 0:00:44 53159.2 0.24 183.9 0.0 result[26] 0:00:44 53222.4 0.23 182.2 0.0 result[14] 0:00:45 53272.3 0.23 181.6 0.0 result[31] 0:00:46 53318.9 0.23 181.2 0.0 result[11] 0:00:47 53315.5 0.23 179.0 0.0 result[2] 0:00:48 53398.7 0.23 177.0 0.0 result[1] 0:00:49 53508.5 0.23 177.0 0.0 result[5] 0:00:50 53578.3 0.22 176.1 0.0 result[21] 0:00:50 53538.4 0.22 176.1 0.0 result[28] 0:00:51 53598.3 0.22 175.4 0.0 result[2] 0:00:52 53658.2 0.22 174.4 0.0 result[0] 0:00:53 53731.3 0.22 173.3 0.0 result[0] 0:00:54 53604.9 0.22 169.4 0.0 result[28] 0:00:55 53664.8 0.22 165.8 0.0 result[15] 0:00:55 53671.5 0.21 165.5 0.0 result[16] 0:00:56 53817.8 0.21 165.6 0.0 result[8] 0:00:57 53954.2 0.21 167.0 0.0 result[21] 0:00:58 53987.5 0.21 166.1 0.0 0:00:59 54030.7 0.21 160.3 0.0 0:00:59 54027.4 0.21 156.7 0.0 0:01:01 54060.7 0.21 151.2 0.0 0:01:01 53914.3 0.21 139.4 0.0 0:01:02 53967.5 0.21 136.1 0.0 0:01:03 54004.1 0.21 134.9 0.0 0:01:04 54010.8 0.21 127.8 0.0 0:01:05 54173.8 0.21 123.5 0.0 0:01:06 54160.4 0.21 113.4 0.0 0:01:07 54127.2 0.21 108.6 0.0 0:01:09 54140.5 0.21 100.7 0.0 0:01:10 54103.9 0.21 88.8 0.0 0:01:11 54207.0 0.21 87.2 0.0 0:01:12 54093.9 0.21 73.1 0.0 0:01:13 54153.8 0.21 71.1 0.0 0:01:14 54074.0 0.21 65.6 0.0 0:01:15 54024.1 0.21 65.3 0.0 0:01:16 54067.3 0.21 63.5 0.0 0:01:17 54060.7 0.21 59.6 0.0 0:01:18 54180.4 0.21 57.7 0.0 0:01:22 54696.0 0.21 52.9 0.0 0:01:27 55367.9 0.21 50.3 0.0 0:01:30 55630.7 0.21 50.0 0.0 0:01:34 53435.3 0.21 53.4 0.0 0:01:34 53435.3 0.21 53.4 0.0 0:01:34 53448.6 0.21 53.6 0.0 Optimization Complete --------------------- WNS: 0.21 TNS: 4.25 Number of Violating Paths: 35 Nets with DRC Violations: 0 Total moveable cell area: 53448.9 Total fixed cell area: 0.0 Core area: (1000 1000 200980 298360) Beginning Coarse Placement (Congestion Driven) --------------------------------------------- Information: Running stand-alone coarse placer in a separate process using temp directory '/tmp'. (PSYN-605) 100% done. 40%...60%...80%...100% done. Coarse Placement Complete -------------------------- [begin initializing data for legality checker] Initializing Data Structure ... Reading technology information ... Technology table contains 6 routable metal layers Top most routable layer is set to be metal4 This is considered as a 4-metal-layer design Reading library information from DB ... Reading misc information ... array has 0 vertical and 59 horizontal rows GRC ref loc X corrected GRC ref loc Y corrected 26 pre-routes for placement blockage/checking 106 pre-routes for map congestion calculation Checking information read in ... design style = Horizontal masters, Horizontal rows Preprocessing design ... splitting rows by natural obstacles ... [end initializing data for legality checker] **************************************** Report : Chip Summary Design : or1200_alu Version: D-2010.03-ICC-SP1 Date : Tue Nov 2 10:27:53 2010 **************************************** Std cell utilization: 89.88% (16068/(17877-0)) (Non-fixed + Fixed) Std cell utilization: 89.88% (16068/(17877-0)) (Non-fixed only) Chip area: 17877 sites, bbox (1.00 1.00 200.98 298.36) um Std cell area: 16068 sites, (non-fixed:16068 fixed:0) 2779 cells, (non-fixed:2779 fixed:0) Macro cell area: 0 sites 0 cells Placement blockages: 0 sites, (excluding fixed std cells) 0 sites, (include fixed std cells & chimney area) 0 sites, (complete p/g net blockages) Routing blockages: 0 sites, (partial p/g net blockages) 0 sites, (routing blockages and signal pre-route) Lib cell count: 112 Avg. std cell width: 5.08 um Site array: unit (width: 0.66 um, height: 5.04 um, rows: 59) Physical DB scale: 1000 db_unit = 1 um **************************************** Report : pnet options Design : or1200_alu Version: D-2010.03-ICC-SP1 Date : Tue Nov 2 10:27:53 2010 **************************************** -------------------------------------------------------------------- Layer Blockage Min_width Min_height Via_additive Density -------------------------------------------------------------------- METAL1 none --- --- via additive --- METAL2 none --- --- via additive --- METAL3 none --- --- via additive --- METAL4 none --- --- via additive --- METAL5 none --- --- via additive --- METAL6 none --- --- via additive --- Legalizing 2779 illegal cells... Starting legalizer. Initial legalization: 100% (0 sec) Optimizations pass 1: 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% (0 sec) Optimizations pass 2: 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% (0 sec) Optimizations pass 3: 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% (0 sec) Legalization complete (1 total sec) **************************************** Report : Legalize Displacement Design : or1200_alu Version: D-2010.03-ICC-SP1 Date : Tue Nov 2 10:27:54 2010 **************************************** avg cell displacement: 1.591 um ( 0.32 row height) max cell displacement: 6.135 um ( 1.22 row height) std deviation: 0.850 um ( 0.17 row height) number of cell moved: 2779 cells (out of 2779 cells) Total 0 cells has large displacement (e.g. > 15.120 um or 3 row height) WNS: 0.19 TNS: 4.26 Number of Violating Paths: 35 Nets with DRC Violations: 0 Total moveable cell area: 53448.9 Total fixed cell area: 0.0 Core area: (1000 1000 200980 298360) Timing and DRC Optimization (Stage 1) -------------------------------------- Beginning Timing Optimizations ------------------------------ ELAPSED WORST NEG TOTAL NEG DESIGN TIME AREA SLACK SLACK RULE COST ENDPOINT --------- --------- --------- --------- --------- ------------------------- 0:01:47 53448.6 0.19 51.2 0.0 0:01:49 53658.2 0.17 50.6 0.0 result[3] 0:01:50 53857.7 0.15 49.9 0.0 result[4] 0:01:51 53854.4 0.15 48.5 0.0 result[5] 0:01:51 53841.1 0.15 48.2 0.0 result[3] 0:01:52 53984.1 0.15 48.6 0.0 result[8] 0:01:54 54047.3 0.14 47.9 0.0 result[4] 0:01:54 54163.8 0.14 47.7 0.0 result[4] 0:01:55 54177.1 0.14 45.8 0.0 result[4] 0:01:56 54187.1 0.14 45.6 0.0 result[3] 0:01:57 54293.5 0.13 45.6 0.0 result[21] 0:01:57 54303.5 0.13 45.0 0.0 result[21] 0:01:58 54416.6 0.13 45.0 0.0 result[15] 0:02:00 54493.1 0.13 44.3 0.0 0:02:01 54589.6 0.13 44.0 0.0 0:02:01 54589.6 0.13 43.8 0.0 0:02:02 54642.8 0.13 43.1 0.0 0:02:03 54629.5 0.13 42.1 0.0 0:02:04 54662.7 0.13 41.4 0.0 0:02:05 54732.6 0.13 40.6 0.0 0:02:06 54772.5 0.13 39.7 0.0 0:02:07 54775.8 0.13 39.0 0.0 0:02:08 54799.1 0.13 36.7 0.0 0:02:08 54855.7 0.13 36.0 0.0 0:02:10 55025.3 0.13 34.3 0.0 0:02:10 55022.0 0.13 34.3 0.0 0:02:11 55088.5 0.13 33.8 0.0 0:02:12 55158.4 0.13 33.2 0.0 0:02:13 55145.1 0.13 32.2 0.0 0:02:14 55165.0 0.13 32.0 0.0 0:02:14 55238.2 0.13 31.4 0.0 0:02:17 55504.3 0.13 30.3 0.0 0:02:21 55976.7 0.13 29.0 0.0 0:02:23 56236.1 0.13 28.6 0.0 result[4] 0:02:24 56236.1 0.13 28.6 0.0 result[3] 0:02:25 56236.1 0.13 28.6 0.0 0:02:28 54938.8 0.13 30.4 0.0 0:02:28 54938.8 0.13 30.4 0.0 0:02:28 54928.8 0.13 30.6 0.0 Optimization Complete --------------------- Placement Optimization (Stage 1) --------------------------------- [begin initializing data for legality checker] Initializing Data Structure ... Reading technology information ... Technology table contains 6 routable metal layers Top most routable layer is set to be metal4 This is considered as a 4-metal-layer design Reading library information from DB ... Reading misc information ... array has 0 vertical and 59 horizontal rows GRC ref loc X corrected GRC ref loc Y corrected 26 pre-routes for placement blockage/checking 106 pre-routes for map congestion calculation Checking information read in ... design style = Horizontal masters, Horizontal rows Preprocessing design ... splitting rows by natural obstacles ... [end initializing data for legality checker] **************************************** Report : Chip Summary Design : or1200_alu Version: D-2010.03-ICC-SP1 Date : Tue Nov 2 10:28:36 2010 **************************************** Std cell utilization: 92.37% (16513/(17877-0)) (Non-fixed + Fixed) Std cell utilization: 92.37% (16513/(17877-0)) (Non-fixed only) Chip area: 17877 sites, bbox (1.00 1.00 200.98 298.36) um Std cell area: 16513 sites, (non-fixed:16513 fixed:0) 2803 cells, (non-fixed:2803 fixed:0) Macro cell area: 0 sites 0 cells Placement blockages: 0 sites, (excluding fixed std cells) 0 sites, (include fixed std cells & chimney area) 0 sites, (complete p/g net blockages) Routing blockages: 0 sites, (partial p/g net blockages) 0 sites, (routing blockages and signal pre-route) Lib cell count: 114 Avg. std cell width: 5.01 um Site array: unit (width: 0.66 um, height: 5.04 um, rows: 59) Physical DB scale: 1000 db_unit = 1 um **************************************** Report : pnet options Design : or1200_alu Version: D-2010.03-ICC-SP1 Date : Tue Nov 2 10:28:36 2010 **************************************** -------------------------------------------------------------------- Layer Blockage Min_width Min_height Via_additive Density -------------------------------------------------------------------- METAL1 none --- --- via additive --- METAL2 none --- --- via additive --- METAL3 none --- --- via additive --- METAL4 none --- --- via additive --- METAL5 none --- --- via additive --- METAL6 none --- --- via additive --- Legalizing 610 illegal cells... Starting legalizer. Initial legalization: 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% (0 sec) Optimizations pass 1: 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% (0 sec) Optimizations pass 2: 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% (0 sec) Optimizations pass 3: 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% (0 sec) Legalization complete (1 total sec) **************************************** Report : Legalize Displacement Design : or1200_alu Version: D-2010.03-ICC-SP1 Date : Tue Nov 2 10:28:37 2010 **************************************** avg cell displacement: 1.500 um ( 0.30 row height) max cell displacement: 12.268 um ( 2.43 row height) std deviation: 1.287 um ( 0.26 row height) number of cell moved: 1277 cells (out of 2803 cells) Total 0 cells has large displacement (e.g. > 15.120 um or 3 row height) Placement Optimization Complete ------------------------------- WNS: 0.14 TNS: 3.13 Number of Violating Paths: 34 Nets with DRC Violations: 0 Total moveable cell area: 54929.1 Total fixed cell area: 0.0 Core area: (1000 1000 200980 298360) Timing and DRC Optimization (Stage 2) -------------------------------------- Beginning Timing Optimizations ------------------------------ ELAPSED WORST NEG TOTAL NEG DESIGN TIME AREA SLACK SLACK RULE COST ENDPOINT --------- --------- --------- --------- --------- ------------------------- 0:02:30 54928.8 0.14 33.8 0.0 0:02:31 54945.5 0.13 33.8 0.0 result[3] 0:02:32 55032.0 0.13 33.7 0.0 result[0] 0:02:33 55041.9 0.13 33.7 0.0 result[3] 0:02:34 55035.3 0.13 33.7 0.0 0:02:34 55038.6 0.13 33.5 0.0 0:02:35 55015.3 0.13 33.4 0.0 0:02:36 55038.6 0.13 33.3 0.0 0:02:36 55038.6 0.13 33.3 0.0 0:02:37 55065.2 0.13 32.9 0.0 0:02:38 55088.5 0.13 32.9 0.0 0:02:39 55111.8 0.13 32.6 0.0 0:02:39 55148.4 0.13 32.2 0.0 0:02:40 55158.4 0.13 32.0 0.0 0:02:41 55148.4 0.13 31.9 0.0 0:02:42 55141.7 0.13 31.7 0.0 0:02:43 55151.7 0.13 31.6 0.0 0:02:44 55185.0 0.13 31.9 0.0 0:02:46 55321.4 0.13 30.0 0.0 0:02:51 55664.0 0.13 29.4 0.0 0:02:53 55827.0 0.13 29.1 0.0 result[8] 0:02:54 55853.6 0.13 29.5 0.0 result[3] 0:02:54 56036.5 0.13 30.9 0.0 result[2] 0:02:55 56209.5 0.12 30.6 0.0 result[0] 0:02:56 56209.5 0.12 30.6 0.0 0:02:59 55394.5 0.17 31.0 0.0 0:02:59 55394.5 0.17 31.0 0.0 0:02:59 55441.1 0.12 30.9 0.0 Optimization Complete --------------------- Placement Optimization (Stage 2) --------------------------------- [begin initializing data for legality checker] Initializing Data Structure ... Reading technology information ... Technology table contains 6 routable metal layers Top most routable layer is set to be metal4 This is considered as a 4-metal-layer design Reading library information from DB ... Reading misc information ... array has 0 vertical and 59 horizontal rows GRC ref loc X corrected GRC ref loc Y corrected 26 pre-routes for placement blockage/checking 106 pre-routes for map congestion calculation Checking information read in ... design style = Horizontal masters, Horizontal rows Preprocessing design ... splitting rows by natural obstacles ... [end initializing data for legality checker] **************************************** Report : Chip Summary Design : or1200_alu Version: D-2010.03-ICC-SP1 Date : Tue Nov 2 10:29:07 2010 **************************************** Std cell utilization: 93.23% (16667/(17877-0)) (Non-fixed + Fixed) Std cell utilization: 93.23% (16667/(17877-0)) (Non-fixed only) Chip area: 17877 sites, bbox (1.00 1.00 200.98 298.36) um Std cell area: 16667 sites, (non-fixed:16667 fixed:0) 2812 cells, (non-fixed:2812 fixed:0) Macro cell area: 0 sites 0 cells Placement blockages: 0 sites, (excluding fixed std cells) 0 sites, (include fixed std cells & chimney area) 0 sites, (complete p/g net blockages) Routing blockages: 0 sites, (partial p/g net blockages) 0 sites, (routing blockages and signal pre-route) Lib cell count: 114 Avg. std cell width: 5.05 um Site array: unit (width: 0.66 um, height: 5.04 um, rows: 59) Physical DB scale: 1000 db_unit = 1 um **************************************** Report : pnet options Design : or1200_alu Version: D-2010.03-ICC-SP1 Date : Tue Nov 2 10:29:07 2010 **************************************** -------------------------------------------------------------------- Layer Blockage Min_width Min_height Via_additive Density -------------------------------------------------------------------- METAL1 none --- --- via additive --- METAL2 none --- --- via additive --- METAL3 none --- --- via additive --- METAL4 none --- --- via additive --- METAL5 none --- --- via additive --- METAL6 none --- --- via additive --- Legalizing 227 illegal cells... Starting legalizer. Initial legalization: 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% (0 sec) Optimizations pass 1: 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% (0 sec) Optimizations pass 2: 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% (0 sec) Optimizations pass 3: 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% (0 sec) Legalization complete (1 total sec) **************************************** Report : Legalize Displacement Design : or1200_alu Version: D-2010.03-ICC-SP1 Date : Tue Nov 2 10:29:08 2010 **************************************** avg cell displacement: 1.501 um ( 0.30 row height) max cell displacement: 14.117 um ( 2.80 row height) std deviation: 1.583 um ( 0.31 row height) number of cell moved: 885 cells (out of 2812 cells) Total 0 cells has large displacement (e.g. > 15.120 um or 3 row height) Placement Optimization Complete ------------------------------- WNS: 0.15 TNS: 3.14 Number of Violating Paths: 34 Nets with DRC Violations: 0 Total moveable cell area: 55441.3 Total fixed cell area: 0.0 Core area: (1000 1000 200980 298360) [begin initializing data for legality checker] Initializing Data Structure ... Reading technology information ... Technology table contains 6 routable metal layers Top most routable layer is set to be metal4 This is considered as a 4-metal-layer design Reading library information from DB ... Reading misc information ... array has 0 vertical and 59 horizontal rows GRC ref loc X corrected GRC ref loc Y corrected 26 pre-routes for placement blockage/checking 106 pre-routes for map congestion calculation Checking information read in ... design style = Horizontal masters, Horizontal rows Preprocessing design ... splitting rows by natural obstacles ... [end initializing data for legality checker] Warning: Die area is not integer multiples of min site height (5040), object's width and height(201980,299360). (PSYN-523) Warning: Die area is not integer multiples of min site width (660), object's width and height(201980,299360). (PSYN-523) **************************************************** Check_legality: Report for Fixed Placement Cells Information: Use the -verbose option to get details about the legality violations. (PSYN-054) **************************************************** (fixed placement) Cells Not on Row : 0 (fixed placement) Cell Overlaps : 0 (fixed placement) Cells overlapping blockages : 0 (fixed placement) Orientation Violations : 0 (fixed placement) Site Violations : 0 (fixed placement) Power Strap Violations : 0 ****************************************************** ****************************************************** Check_legality: Report for Non-fixed Placement Cells Information: Use the -verbose option to get details about the legality violations. (PSYN-054) ****************************************************** Number of Cells Not on Row : 0 Number of Cell Overlaps : 0 Number of Cells overlapping blockages : 0 Number of Orientation Violations : 0 Number of Site Violations : 0 Number of Power Strap Violations : 0 ******************************************** Information: Updating database... Loading design 'or1200_alu' Information: Library Manufacturing Grid(GridResolution) : 5 Information: Time Unit from Milkyway design library: 'ns' Information: Design Library and main library timing units are matched - 1.000 ns. Information: Resistance Unit from Milkyway design library: 'kohm' Information: Design Library and main library resistance units are matched - 1.000 kohm. Information: Capacitance Unit from Milkyway design library: 'pf' Information: Design Library and main library capacitance units are matched - 1.000 pf. Information: Layer METAL1 is ignored for resistance and capacitance computation. (RCEX-019) Information: Layer METAL5 is ignored for resistance and capacitance computation. (RCEX-019) Information: Layer METAL6 is ignored for resistance and capacitance computation. (RCEX-019) **************************************************************** Information: TLUPlus based RC computation is enabled. (RCEX-141) **************************************************************** Information: The distance unit in Capacitance and Resistance is 1 micron. (RCEX-007) Information: The RC model used is TLU+. (RCEX-015) Information: Library Derived Cap for layer METAL1 : 0.00021 0.00021 (RCEX-011) Information: Library Derived Res for layer METAL1 : 0.00044 0.00044 (RCEX-011) Information: Library Derived Cap for layer METAL2 : 0.0002 0.0002 (RCEX-011) Information: Library Derived Res for layer METAL2 : 0.00036 0.00036 (RCEX-011) Information: Library Derived Cap for layer METAL3 : 0.00024 0.00024 (RCEX-011) Information: Library Derived Res for layer METAL3 : 0.00036 0.00036 (RCEX-011) Information: Library Derived Cap for layer METAL4 : 0.0002 0.0002 (RCEX-011) Information: Library Derived Res for layer METAL4 : 0.00036 0.00036 (RCEX-011) Information: Library Derived Cap for layer METAL5 : 0.00021 0.00021 (RCEX-011) Information: Library Derived Res for layer METAL5 : 0.00036 0.00036 (RCEX-011) Information: Library Derived Cap for layer METAL6 : 0.00027 0.00027 (RCEX-011) Information: Library Derived Res for layer METAL6 : 0.0001 0.0001 (RCEX-011) Information: Library Derived Horizontal Cap : 0.00024 0.00024 (RCEX-011) Information: Library Derived Horizontal Res : 0.00036 0.00036 (RCEX-011) Information: Library Derived Vertical Cap : 0.0002 0.0002 (RCEX-011) Information: Library Derived Vertical Res : 0.00036 0.00036 (RCEX-011) Information: Using derived R and C coefficients. (RCEX-008) Information: Using region-based R and C coefficients. (RCEX-013) Information: Library Derived Via Res : 0.0064 0.0064 (RCEX-011) Legalizing Placement -------------------- [begin initializing data for legality checker] Initializing Data Structure ... Reading technology information ... Technology table contains 6 routable metal layers Top most routable layer is set to be metal4 This is considered as a 4-metal-layer design Reading library information from DB ... Reading misc information ... array has 0 vertical and 59 horizontal rows GRC ref loc X corrected GRC ref loc Y corrected 26 pre-routes for placement blockage/checking 106 pre-routes for map congestion calculation Checking information read in ... design style = Horizontal masters, Horizontal rows Preprocessing design ... splitting rows by natural obstacles ... [end initializing data for legality checker] **************************************** Report : Chip Summary Design : or1200_alu Version: D-2010.03-ICC-SP1 Date : Tue Nov 2 10:29:11 2010 **************************************** Std cell utilization: 93.23% (16667/(17877-0)) (Non-fixed + Fixed) Std cell utilization: 93.23% (16667/(17877-0)) (Non-fixed only) Chip area: 17877 sites, bbox (1.00 1.00 200.98 298.36) um Std cell area: 16667 sites, (non-fixed:16667 fixed:0) 2812 cells, (non-fixed:2812 fixed:0) Macro cell area: 0 sites 0 cells Placement blockages: 0 sites, (excluding fixed std cells) 0 sites, (include fixed std cells & chimney area) 0 sites, (complete p/g net blockages) Routing blockages: 0 sites, (partial p/g net blockages) 0 sites, (routing blockages and signal pre-route) Lib cell count: 114 Avg. std cell width: 5.05 um Site array: unit (width: 0.66 um, height: 5.04 um, rows: 59) Physical DB scale: 1000 db_unit = 1 um **************************************** Report : pnet options Design : or1200_alu Version: D-2010.03-ICC-SP1 Date : Tue Nov 2 10:29:11 2010 **************************************** -------------------------------------------------------------------- Layer Blockage Min_width Min_height Via_additive Density -------------------------------------------------------------------- METAL1 none --- --- via additive --- METAL2 none --- --- via additive --- METAL3 none --- --- via additive --- METAL4 none --- --- via additive --- METAL5 none --- --- via additive --- METAL6 none --- --- via additive --- **************************************** Report : Legalize Displacement Design : or1200_alu Version: D-2010.03-ICC-SP1 Date : Tue Nov 2 10:29:11 2010 **************************************** No cell displacement. Placement Legalization Complete ------------------------------- [begin initializing data for legality checker] Initializing Data Structure ... Reading technology information ... Technology table contains 6 routable metal layers Top most routable layer is set to be metal4 This is considered as a 4-metal-layer design Reading library information from DB ... Reading misc information ... array has 0 vertical and 59 horizontal rows GRC ref loc X corrected GRC ref loc Y corrected 26 pre-routes for placement blockage/checking 106 pre-routes for map congestion calculation Checking information read in ... design style = Horizontal masters, Horizontal rows Preprocessing design ... splitting rows by natural obstacles ... [end initializing data for legality checker] Warning: Die area is not integer multiples of min site height (5040), object's width and height(201980,299360). (PSYN-523) Warning: Die area is not integer multiples of min site width (660), object's width and height(201980,299360). (PSYN-523) **************************************************** Check_legality: Report for Fixed Placement Cells Information: Use the -verbose option to get details about the legality violations. (PSYN-054) **************************************************** (fixed placement) Cells Not on Row : 0 (fixed placement) Cell Overlaps : 0 (fixed placement) Cells overlapping blockages : 0 (fixed placement) Orientation Violations : 0 (fixed placement) Site Violations : 0 (fixed placement) Power Strap Violations : 0 ****************************************************** ****************************************************** Check_legality: Report for Non-fixed Placement Cells Information: Use the -verbose option to get details about the legality violations. (PSYN-054) ****************************************************** Number of Cells Not on Row : 0 Number of Cell Overlaps : 0 Number of Cells overlapping blockages : 0 Number of Orientation Violations : 0 Number of Site Violations : 0 Number of Power Strap Violations : 0 ******************************************** Information: Updating database... Information: Performing CEL netlist consistency check. (MWDC-118) Information: CEL consistency check PASSED. (MWDC-119) Info: Writing NID in 3.0 format Info: Writing NID in 3.0 format Information: Saved design named or1200_alu. (UIG-5) Info: Writing NID in 3.0 format Info: Writing NID in 3.0 format Information: Saved design named or1200_alu_placement_done. (UIG-5) preroute_standard_cells Prerouting standard cells vertically: [10.03%] [20.06%] [30.09%] [40.11%] [50.14%] [60.17%] [70.20%] [80.23%] [90.26%] [100.00%] [done] [Prerouter] CPU = 0:00:00, Elapsed = 0:00:00 Peak Memory = 150M Data = 0M next: update_pg begin derive_pg_connection... --- connected 2812 power ports and 2812 ground ports Prerouting standard cells horizontally: [12.59%] [22.62%] [33.71%] [46.69%] [57.40%] [68.46%] [78.88%] [92.50%] [100.00%] [done] [Prerouter] CPU = 0:00:00, Elapsed = 0:00:00 Peak Memory = 150M Data = 0M next: update_pg Information: PG PORT PUNCHING: Number of top ports created/deleted: 2 (MW-336) Information: PG PORT PUNCHING: Number of ports connected: 5624 (MW-337) Information: PG PORT PUNCHING: Total number of changes: 5626 (MW-339) begin derive_pg_connection... --- connected 2812 power ports and 2812 ground ports Information: Performing CEL netlist consistency check. (MWDC-118) Information: CEL consistency check PASSED. (MWDC-119) Info: Writing NID in 3.0 format Info: Writing NID in 3.0 format Information: linking reference library : /home/projects/courses/fall_10/ee382m-16947/Artisan/sc/apollo/tsmc18. (PSYN-878) Linking design 'or1200_alu' Using the following designs and libraries: -------------------------------------------------------------------------- or1200_alu or1200_alu.CEL typical (library) /home/projects/courses/fall_10/ee382m-16947/Artisan/synopsys/typical.db Information: The design has horizontal rows, and Y-symmetry has been used for sites. (MWDC-217) Floorplan loading succeeded. Load global CTS reference options from NID to stack Info: Writing NID in 3.0 format Info: Writing NID in 3.0 format Information: Saved design named or1200_alu_preroute_standard_cells. (UIG-5) create_preroute_vias Totally 0 vias are created [Prerouter] CPU = 0:00:00, Elapsed = 0:00:00 Peak Memory = 150M Data = 0M Totally 0 vias are created [Prerouter] CPU = 0:00:00, Elapsed = 0:00:00 Peak Memory = 150M Data = 0M next: update_pg begin derive_pg_connection... --- connected 2812 power ports and 2812 ground ports about to run psynopt Loading design 'or1200_alu' Information: Library Manufacturing Grid(GridResolution) : 5 Information: Time Unit from Milkyway design library: 'ns' Information: Design Library and main library timing units are matched - 1.000 ns. Information: Resistance Unit from Milkyway design library: 'kohm' Information: Design Library and main library resistance units are matched - 1.000 kohm. Information: Capacitance Unit from Milkyway design library: 'pf' Information: Design Library and main library capacitance units are matched - 1.000 pf. Information: Layer METAL1 is ignored for resistance and capacitance computation. (RCEX-019) Information: Layer METAL5 is ignored for resistance and capacitance computation. (RCEX-019) Information: Layer METAL6 is ignored for resistance and capacitance computation. (RCEX-019) **************************************************************** Information: TLUPlus based RC computation is enabled. (RCEX-141) **************************************************************** Information: The distance unit in Capacitance and Resistance is 1 micron. (RCEX-007) Information: The RC model used is TLU+. (RCEX-015) Information: Library Derived Cap for layer METAL1 : 0.00021 0.00021 (RCEX-011) Information: Library Derived Res for layer METAL1 : 0.00044 0.00044 (RCEX-011) Information: Library Derived Cap for layer METAL2 : 0.0002 0.0002 (RCEX-011) Information: Library Derived Res for layer METAL2 : 0.00036 0.00036 (RCEX-011) Information: Library Derived Cap for layer METAL3 : 0.00024 0.00024 (RCEX-011) Information: Library Derived Res for layer METAL3 : 0.00036 0.00036 (RCEX-011) Information: Library Derived Cap for layer METAL4 : 0.0002 0.0002 (RCEX-011) Information: Library Derived Res for layer METAL4 : 0.00036 0.00036 (RCEX-011) Information: Library Derived Cap for layer METAL5 : 0.00021 0.00021 (RCEX-011) Information: Library Derived Res for layer METAL5 : 0.00036 0.00036 (RCEX-011) Information: Library Derived Cap for layer METAL6 : 0.00027 0.00027 (RCEX-011) Information: Library Derived Res for layer METAL6 : 0.0001 0.0001 (RCEX-011) Information: Library Derived Horizontal Cap : 0.00024 0.00024 (RCEX-011) Information: Library Derived Horizontal Res : 0.00036 0.00036 (RCEX-011) Information: Library Derived Vertical Cap : 0.0002 0.0002 (RCEX-011) Information: Library Derived Vertical Res : 0.00036 0.00036 (RCEX-011) Information: Using derived R and C coefficients. (RCEX-008) Information: Using region-based R and C coefficients. (RCEX-013) Information: Library Derived Via Res : 0.0064 0.0064 (RCEX-011) WNS: 0.15 TNS: 3.16 Number of Violating Paths: 34 Nets with DRC Violations: 0 Total moveable cell area: 55441.5 Total fixed cell area: 0.0 Core area: (1000 1000 200980 298360) Timing and DRC Optimization (Stage 1) -------------------------------------- Beginning Timing Optimizations ------------------------------ ELAPSED WORST NEG TOTAL NEG DESIGN TIME AREA SLACK SLACK RULE COST ENDPOINT --------- --------- --------- --------- --------- ------------------------- 0:00:02 55441.1 0.15 30.2 0.0 0:00:04 55491.0 0.13 30.3 0.0 result[0] 0:00:04 55570.8 0.13 30.5 0.0 result[3] 0:00:05 55574.2 0.13 30.7 0.0 0:00:06 55497.7 0.13 30.6 0.0 0:00:07 55497.7 0.13 30.6 0.0 0:00:08 55487.7 0.13 30.5 0.0 0:00:09 55441.1 0.13 30.5 0.0 0:00:09 55421.2 0.13 30.5 0.0 0:00:10 55387.9 0.13 30.0 0.0 0:00:11 55394.5 0.13 29.9 0.0 0:00:12 55424.5 0.13 29.3 0.0 0:00:13 55530.9 0.13 29.2 0.0 0:00:14 55667.3 0.13 28.9 0.0 0:00:15 55753.8 0.13 28.5 0.0 0:00:16 55763.8 0.13 28.5 0.0 0:00:17 55820.3 0.13 28.4 0.0 0:00:18 55913.5 0.13 28.6 0.0 0:00:19 55976.7 0.13 28.5 0.0 0:00:20 55976.7 0.13 28.5 0.0 0:00:21 56039.9 0.13 27.5 0.0 0:00:22 56083.1 0.13 26.4 0.0 0:00:23 56139.7 0.13 26.4 0.0 0:00:24 56249.4 0.13 26.0 0.0 0:00:25 56212.8 0.13 26.0 0.0 0:00:25 56242.8 0.13 26.1 0.0 0:00:27 56409.1 0.12 26.4 0.0 result[2] 0:00:28 56405.8 0.12 26.7 0.0 result[5] 0:00:28 56402.4 0.12 26.9 0.0 result[20] 0:00:29 56375.8 0.11 27.0 0.0 result[5] 0:00:30 56369.2 0.11 27.0 0.0 0:00:31 56262.7 0.11 26.5 0.0 0:00:32 56216.2 0.11 26.4 0.0 0:00:32 56146.3 0.11 26.2 0.0 0:00:33 56123.0 0.11 26.2 0.0 0:00:34 56056.5 0.11 26.1 0.0 0:00:35 56013.2 0.11 26.2 0.0 0:00:35 55966.7 0.11 26.2 0.0 Optimization Complete --------------------- Placement Optimization (Stage 1) --------------------------------- [begin initializing data for legality checker] Initializing Data Structure ... Reading technology information ... Technology table contains 6 routable metal layers Top most routable layer is set to be metal4 This is considered as a 4-metal-layer design Reading library information from DB ... Reading misc information ... array has 0 vertical and 59 horizontal rows GRC ref loc X corrected GRC ref loc Y corrected 26 pre-routes for placement blockage/checking 986 pre-routes for map congestion calculation Checking information read in ... design style = Horizontal masters, Horizontal rows Preprocessing design ... splitting rows by natural obstacles ... [end initializing data for legality checker] **************************************** Report : Chip Summary Design : or1200_alu Version: D-2010.03-ICC-SP1 Date : Tue Nov 2 10:29:51 2010 **************************************** Std cell utilization: 94.12% (16825/(17877-0)) (Non-fixed + Fixed) Std cell utilization: 94.12% (16825/(17877-0)) (Non-fixed only) Chip area: 17877 sites, bbox (1.00 1.00 200.98 298.36) um Std cell area: 16825 sites, (non-fixed:16825 fixed:0) 2849 cells, (non-fixed:2849 fixed:0) Macro cell area: 0 sites 0 cells Placement blockages: 0 sites, (excluding fixed std cells) 0 sites, (include fixed std cells & chimney area) 0 sites, (complete p/g net blockages) Routing blockages: 0 sites, (partial p/g net blockages) 0 sites, (routing blockages and signal pre-route) Lib cell count: 114 Avg. std cell width: 5.06 um Site array: unit (width: 0.66 um, height: 5.04 um, rows: 59) Physical DB scale: 1000 db_unit = 1 um **************************************** Report : pnet options Design : or1200_alu Version: D-2010.03-ICC-SP1 Date : Tue Nov 2 10:29:51 2010 **************************************** -------------------------------------------------------------------- Layer Blockage Min_width Min_height Via_additive Density -------------------------------------------------------------------- METAL1 none --- --- via additive --- METAL2 none --- --- via additive --- METAL3 none --- --- via additive --- METAL4 none --- --- via additive --- METAL5 none --- --- via additive --- METAL6 none --- --- via additive --- Legalizing 306 illegal cells... Starting legalizer. Initial legalization: 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% (0 sec) Optimizations pass 1: 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% (0 sec) Optimizations pass 2: 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% (0 sec) Optimizations pass 3: 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% (0 sec) Legalization complete (1 total sec) **************************************** Report : Legalize Displacement Design : or1200_alu Version: D-2010.03-ICC-SP1 Date : Tue Nov 2 10:29:52 2010 **************************************** avg cell displacement: 1.580 um ( 0.31 row height) max cell displacement: 12.227 um ( 2.43 row height) std deviation: 1.385 um ( 0.27 row height) number of cell moved: 1050 cells (out of 2849 cells) Total 0 cells has large displacement (e.g. > 15.120 um or 3 row height) Placement Optimization Complete ------------------------------- WNS: 0.12 TNS: 2.70 Number of Violating Paths: 34 Nets with DRC Violations: 0 Total moveable cell area: 55967.0 Total fixed cell area: 0.0 Core area: (1000 1000 200980 298360) Timing and DRC Optimization (Stage 2) -------------------------------------- Beginning Timing Optimizations ------------------------------ ELAPSED WORST NEG TOTAL NEG DESIGN TIME AREA SLACK SLACK RULE COST ENDPOINT --------- --------- --------- --------- --------- ------------------------- 0:00:38 55966.7 0.12 29.5 0.0 0:00:38 55956.7 0.12 29.4 0.0 result[5] 0:00:39 55943.4 0.12 29.4 0.0 0:00:40 55863.6 0.12 29.2 0.0 0:00:41 55827.0 0.12 29.2 0.0 0:00:42 55807.0 0.12 29.1 0.0 0:00:42 55773.7 0.12 29.1 0.0 0:00:44 55803.7 0.12 29.0 0.0 0:00:44 55813.7 0.12 28.9 0.0 0:00:45 55880.2 0.12 28.5 0.0 0:00:46 55883.5 0.12 28.4 0.0 0:00:47 55946.7 0.12 28.3 0.0 0:00:48 56019.9 0.12 28.0 0.0 0:00:49 56036.5 0.12 28.0 0.0 0:00:51 56119.7 0.12 27.9 0.0 0:00:52 56176.2 0.12 27.6 0.0 0:00:53 56199.5 0.12 27.7 0.0 0:00:54 56212.8 0.12 27.6 0.0 0:00:55 56256.1 0.12 27.3 0.0 0:00:56 56372.5 0.12 27.3 0.0 0:00:57 56432.4 0.12 27.1 0.0 0:00:58 56478.9 0.12 27.0 0.0 0:00:59 56505.6 0.12 26.8 0.0 result[4] 0:01:00 56475.6 0.12 26.7 0.0 0:01:01 56355.9 0.12 26.6 0.0 0:01:02 56322.6 0.12 26.5 0.0 0:01:03 56312.6 0.12 26.5 0.0 0:01:04 56292.7 0.12 26.5 0.0 0:01:05 56282.7 0.12 26.5 0.0 0:01:05 56239.4 0.12 26.5 0.0 0:01:05 56239.4 0.12 26.5 0.0 0:01:05 56239.4 0.12 26.5 0.0 Optimization Complete --------------------- Placement Optimization (Stage 2) --------------------------------- [begin initializing data for legality checker] Initializing Data Structure ... Reading technology information ... Technology table contains 6 routable metal layers Top most routable layer is set to be metal4 This is considered as a 4-metal-layer design Reading library information from DB ... Reading misc information ... array has 0 vertical and 59 horizontal rows GRC ref loc X corrected GRC ref loc Y corrected 26 pre-routes for placement blockage/checking 986 pre-routes for map congestion calculation Checking information read in ... design style = Horizontal masters, Horizontal rows Preprocessing design ... splitting rows by natural obstacles ... [end initializing data for legality checker] **************************************** Report : Chip Summary Design : or1200_alu Version: D-2010.03-ICC-SP1 Date : Tue Nov 2 10:30:21 2010 **************************************** Std cell utilization: 94.57% (16907/(17877-0)) (Non-fixed + Fixed) Std cell utilization: 94.57% (16907/(17877-0)) (Non-fixed only) Chip area: 17877 sites, bbox (1.00 1.00 200.98 298.36) um Std cell area: 16907 sites, (non-fixed:16907 fixed:0) 2862 cells, (non-fixed:2862 fixed:0) Macro cell area: 0 sites 0 cells Placement blockages: 0 sites, (excluding fixed std cells) 0 sites, (include fixed std cells & chimney area) 0 sites, (complete p/g net blockages) Routing blockages: 0 sites, (partial p/g net blockages) 0 sites, (routing blockages and signal pre-route) Lib cell count: 117 Avg. std cell width: 4.99 um Site array: unit (width: 0.66 um, height: 5.04 um, rows: 59) Physical DB scale: 1000 db_unit = 1 um **************************************** Report : pnet options Design : or1200_alu Version: D-2010.03-ICC-SP1 Date : Tue Nov 2 10:30:21 2010 **************************************** -------------------------------------------------------------------- Layer Blockage Min_width Min_height Via_additive Density -------------------------------------------------------------------- METAL1 none --- --- via additive --- METAL2 none --- --- via additive --- METAL3 none --- --- via additive --- METAL4 none --- --- via additive --- METAL5 none --- --- via additive --- METAL6 none --- --- via additive --- Legalizing 185 illegal cells... Starting legalizer. Initial legalization: 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% (0 sec) Optimizations pass 1: 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% (0 sec) Optimizations pass 2: 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% (0 sec) Optimizations pass 3: 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% (0 sec) Legalization complete (1 total sec) **************************************** Report : Legalize Displacement Design : or1200_alu Version: D-2010.03-ICC-SP1 Date : Tue Nov 2 10:30:22 2010 **************************************** avg cell displacement: 1.656 um ( 0.33 row height) max cell displacement: 10.273 um ( 2.04 row height) std deviation: 1.227 um ( 0.24 row height) number of cell moved: 825 cells (out of 2862 cells) Total 0 cells has large displacement (e.g. > 15.120 um or 3 row height) Placement Optimization Complete ------------------------------- WNS: 0.12 TNS: 2.63 Number of Violating Paths: 34 Nets with DRC Violations: 0 Total moveable cell area: 56239.8 Total fixed cell area: 0.0 Core area: (1000 1000 200980 298360) Timing and DRC Optimization (Stage 3) -------------------------------------- Beginning Timing Optimizations ------------------------------ ELAPSED WORST NEG TOTAL NEG DESIGN TIME AREA SLACK SLACK RULE COST ENDPOINT --------- --------- --------- --------- --------- ------------------------- 0:01:08 56239.4 0.12 28.1 0.0 0:01:09 56236.1 0.12 28.1 0.0 0:01:09 56209.5 0.12 28.0 0.0 0:01:10 56209.5 0.12 28.0 0.0 0:01:11 56199.5 0.12 28.0 0.0 0:01:12 56196.2 0.12 28.0 0.0 0:01:13 56219.5 0.12 28.0 0.0 0:01:14 56226.1 0.12 28.0 0.0 0:01:15 56252.8 0.12 27.9 0.0 0:01:16 56306.0 0.12 27.8 0.0 0:01:17 56306.0 0.12 27.8 0.0 0:01:18 56339.2 0.12 27.7 0.0 0:01:19 56342.6 0.12 27.7 0.0 0:01:20 56392.5 0.12 27.4 0.0 0:01:22 56382.5 0.12 27.7 0.0 0:01:22 56402.4 0.12 27.4 0.0 0:01:23 56415.7 0.12 27.3 0.0 0:01:24 56492.3 0.12 27.2 0.0 0:01:25 56558.8 0.12 27.2 0.0 0:01:27 56651.9 0.12 26.6 0.0 0:01:28 56738.4 0.12 25.8 0.0 0:01:29 56798.3 0.11 25.6 0.0 result[0] 0:01:30 56731.8 0.11 25.4 0.0 0:01:31 56648.6 0.11 25.4 0.0 0:01:31 56592.0 0.11 25.3 0.0 0:01:32 56582.1 0.11 25.3 0.0 0:01:33 56562.1 0.11 25.3 0.0 0:01:34 56542.1 0.11 25.3 0.0 0:01:35 56535.5 0.11 25.3 0.0 0:01:35 56525.5 0.11 25.4 0.0 0:01:36 56525.5 0.11 25.4 0.0 0:01:36 56525.5 0.11 25.4 0.0 0:01:37 56449.0 0.11 25.7 0.0 0:01:37 56449.0 0.11 25.7 0.0 0:01:37 56449.0 0.11 25.7 0.0 Optimization Complete --------------------- Placement Optimization (Stage 3) --------------------------------- [begin initializing data for legality checker] Initializing Data Structure ... Reading technology information ... Technology table contains 6 routable metal layers Top most routable layer is set to be metal4 This is considered as a 4-metal-layer design Reading library information from DB ... Reading misc information ... array has 0 vertical and 59 horizontal rows GRC ref loc X corrected GRC ref loc Y corrected 26 pre-routes for placement blockage/checking 986 pre-routes for map congestion calculation Checking information read in ... design style = Horizontal masters, Horizontal rows Preprocessing design ... splitting rows by natural obstacles ... [end initializing data for legality checker] **************************************** Report : Chip Summary Design : or1200_alu Version: D-2010.03-ICC-SP1 Date : Tue Nov 2 10:30:53 2010 **************************************** Std cell utilization: 94.93% (16970/(17877-0)) (Non-fixed + Fixed) Std cell utilization: 94.93% (16970/(17877-0)) (Non-fixed only) Chip area: 17877 sites, bbox (1.00 1.00 200.98 298.36) um Std cell area: 16970 sites, (non-fixed:16970 fixed:0) 2876 cells, (non-fixed:2876 fixed:0) Macro cell area: 0 sites 0 cells Placement blockages: 0 sites, (excluding fixed std cells) 0 sites, (include fixed std cells & chimney area) 0 sites, (complete p/g net blockages) Routing blockages: 0 sites, (partial p/g net blockages) 0 sites, (routing blockages and signal pre-route) Lib cell count: 118 Avg. std cell width: 4.96 um Site array: unit (width: 0.66 um, height: 5.04 um, rows: 59) Physical DB scale: 1000 db_unit = 1 um **************************************** Report : pnet options Design : or1200_alu Version: D-2010.03-ICC-SP1 Date : Tue Nov 2 10:30:53 2010 **************************************** -------------------------------------------------------------------- Layer Blockage Min_width Min_height Via_additive Density -------------------------------------------------------------------- METAL1 none --- --- via additive --- METAL2 none --- --- via additive --- METAL3 none --- --- via additive --- METAL4 none --- --- via additive --- METAL5 none --- --- via additive --- METAL6 none --- --- via additive --- Legalizing 162 illegal cells... Starting legalizer. Initial legalization: 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% (0 sec) Optimizations pass 1: 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% (0 sec) Optimizations pass 2: 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% (0 sec) Optimizations pass 3: 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% (0 sec) Legalization complete (1 total sec) **************************************** Report : Legalize Displacement Design : or1200_alu Version: D-2010.03-ICC-SP1 Date : Tue Nov 2 10:30:54 2010 **************************************** avg cell displacement: 1.689 um ( 0.34 row height) max cell displacement: 10.606 um ( 2.10 row height) std deviation: 1.317 um ( 0.26 row height) number of cell moved: 936 cells (out of 2876 cells) Total 0 cells has large displacement (e.g. > 15.120 um or 3 row height) Placement Optimization Complete ------------------------------- WNS: 0.12 TNS: 2.52 Number of Violating Paths: 34 Nets with DRC Violations: 0 Total moveable cell area: 56449.3 Total fixed cell area: 0.0 Core area: (1000 1000 200980 298360) [begin initializing data for legality checker] Initializing Data Structure ... Reading technology information ... Technology table contains 6 routable metal layers Top most routable layer is set to be metal4 This is considered as a 4-metal-layer design Reading library information from DB ... Reading misc information ... array has 0 vertical and 59 horizontal rows GRC ref loc X corrected GRC ref loc Y corrected 26 pre-routes for placement blockage/checking 986 pre-routes for map congestion calculation Checking information read in ... design style = Horizontal masters, Horizontal rows Preprocessing design ... splitting rows by natural obstacles ... [end initializing data for legality checker] Warning: Die area is not integer multiples of min site height (5040), object's width and height(201980,299360). (PSYN-523) Warning: Die area is not integer multiples of min site width (660), object's width and height(201980,299360). (PSYN-523) **************************************************** Check_legality: Report for Fixed Placement Cells Information: Use the -verbose option to get details about the legality violations. (PSYN-054) **************************************************** (fixed placement) Cells Not on Row : 0 (fixed placement) Cell Overlaps : 0 (fixed placement) Cells overlapping blockages : 0 (fixed placement) Orientation Violations : 0 (fixed placement) Site Violations : 0 (fixed placement) Power Strap Violations : 0 ****************************************************** ****************************************************** Check_legality: Report for Non-fixed Placement Cells Information: Use the -verbose option to get details about the legality violations. (PSYN-054) ****************************************************** Number of Cells Not on Row : 0 Number of Cell Overlaps : 0 Number of Cells overlapping blockages : 0 Number of Orientation Violations : 0 Number of Site Violations : 0 Number of Power Strap Violations : 0 ******************************************** Information: Updating database... about to run route_opt Information: Running detail route with timing driven mode save after iteration 1 (route_opt default). (ROPT-020) ROPT: route_opt strategy for the design: ROPT: Stage : auto ROPT: Effort : medium ROPT: Power mode : none ROPT: Search-Repair loops : 10 ROPT: ECO Search-Repair loops : 4 ROPT: Fix Hold Mode : route_based ROPT: Route Violation threshold : 3000 Routeopt: Using zrt router Information: Running global route with timing driven mode true (route_opt default). (ROPT-020) Information: Running track_assign with timing driven mode true (route_opt default). (ROPT-020) Information: Running detail route with timing driven mode true (route_opt default). (ROPT-020) Loading design 'or1200_alu' Information: Library Manufacturing Grid(GridResolution) : 5 Information: Time Unit from Milkyway design library: 'ns' Information: Design Library and main library timing units are matched - 1.000 ns. Information: Resistance Unit from Milkyway design library: 'kohm' Information: Design Library and main library resistance units are matched - 1.000 kohm. Information: Capacitance Unit from Milkyway design library: 'pf' Information: Design Library and main library capacitance units are matched - 1.000 pf. Information: None of the nets in the design are routed. Estimation of all the nets will be performed. (RCEX-203) Information: Start rc update... Information: Layer METAL1 is ignored for resistance and capacitance computation. (RCEX-019) Information: Layer METAL5 is ignored for resistance and capacitance computation. (RCEX-019) Information: Layer METAL6 is ignored for resistance and capacitance computation. (RCEX-019) **************************************************************** Information: TLUPlus based RC computation is enabled. (RCEX-141) **************************************************************** Information: The distance unit in Capacitance and Resistance is 1 micron. (RCEX-007) Information: The RC model used is TLU+. (RCEX-015) Information: Library Derived Cap for layer METAL1 : 0.00021 0.00021 (RCEX-011) Information: Library Derived Res for layer METAL1 : 0.00044 0.00044 (RCEX-011) Information: Library Derived Cap for layer METAL2 : 0.0002 0.0002 (RCEX-011) Information: Library Derived Res for layer METAL2 : 0.00036 0.00036 (RCEX-011) Information: Library Derived Cap for layer METAL3 : 0.00024 0.00024 (RCEX-011) Information: Library Derived Res for layer METAL3 : 0.00036 0.00036 (RCEX-011) Information: Library Derived Cap for layer METAL4 : 0.0002 0.0002 (RCEX-011) Information: Library Derived Res for layer METAL4 : 0.00036 0.00036 (RCEX-011) Information: Library Derived Cap for layer METAL5 : 0.00021 0.00021 (RCEX-011) Information: Library Derived Res for layer METAL5 : 0.00036 0.00036 (RCEX-011) Information: Library Derived Cap for layer METAL6 : 0.00027 0.00027 (RCEX-011) Information: Library Derived Res for layer METAL6 : 0.0001 0.0001 (RCEX-011) Information: Library Derived Horizontal Cap : 0.00024 0.00024 (RCEX-011) Information: Library Derived Horizontal Res : 0.00036 0.00036 (RCEX-011) Information: Library Derived Vertical Cap : 0.0002 0.0002 (RCEX-011) Information: Library Derived Vertical Res : 0.00036 0.00036 (RCEX-011) Information: Using derived R and C coefficients. (RCEX-008) Information: Using region-based R and C coefficients. (RCEX-013) Information: Library Derived Via Res : 0.0064 0.0064 (RCEX-011) Information: End rc update. Information: Updating design information... (UID-85) GART: Updated design time. GART: Transferring timing data to the router.... GART: Done transferring timing data to the router. Information: Running global route with timing driven mode true (route_opt default). (ROPT-020) Information: Running track_assign with timing driven mode true (route_opt default). (ROPT-020) Information: Running detail route with timing driven mode true (route_opt default). (ROPT-020) ROPT: Running Initial Route Tue Nov 2 10:30:58 2010 Beginning initial routing -------------------------- Turn off antenna since no rule is specified Cell Min-Routing-Layer = METAL2 Cell Max-Routing-Layer = METAL4 Start Global Route ... [Init] Elapsed real time: 0:00:00 [Init] Elapsed cpu time: sys=0:00:00 usr=0:00:00 total=0:00:00 [Init] Stage (MB): Used 0 Alloctr 0 Proc 0 [Init] Total (MB): Used 8 Alloctr 8 Proc 417 Printing options for 'set_route_zrt_common_options' Printing options for 'set_route_zrt_global_options' -timing_driven : true Begin global routing. Constructing data structure ... Design statistics: Design Bounding Box (0.00,0.00,201.98,299.36) Number of routing layers = 6 layer METAL1, dir Hor, min width = 0.23, min space = 0.23 pitch = 0.56 layer METAL2, dir Ver, min width = 0.28, min space = 0.28 pitch = 0.66 layer METAL3, dir Hor, min width = 0.28, min space = 0.28 pitch = 0.56 layer METAL4, dir Ver, min width = 0.28, min space = 0.28 pitch = 0.66 layer METAL5, dir Hor, min width = 0.28, min space = 0.28 pitch = 0.61 layer METAL6, dir Ver, min width = 0.44, min space = 0.46 pitch = 0.95 Current Stage stats: [End of Build Tech Data] Elapsed real time: 0:00:00 [End of Build Tech Data] Elapsed cpu time: sys=0:00:00 usr=0:00:00 total=0:00:00 [End of Build Tech Data] Stage (MB): Used 0 Alloctr 0 Proc 0 [End of Build Tech Data] Total (MB): Used 9 Alloctr 9 Proc 417 Net statistics: Total number of nets = 2998 Number of nets to route = 2996 2 nets are fully connected, of which 2 are detail routed and 0 are global routed. Current Stage stats: [End of Build All Nets] Elapsed real time: 0:00:00 [End of Build All Nets] Elapsed cpu time: sys=0:00:00 usr=0:00:00 total=0:00:00 [End of Build All Nets] Stage (MB): Used 0 Alloctr 0 Proc 0 [End of Build All Nets] Total (MB): Used 9 Alloctr 9 Proc 417 Average gCell capacity 0.00 on layer (1) METAL1 Average gCell capacity 7.17 on layer (2) METAL2 Average gCell capacity 7.46 on layer (3) METAL3 Average gCell capacity 7.16 on layer (4) METAL4 Average gCell capacity 0.00 on layer (5) METAL5 Average gCell capacity 0.00 on layer (6) METAL6 Average number of tracks per gCell 8.79 on layer (1) METAL1 Average number of tracks per gCell 7.85 on layer (2) METAL2 Average number of tracks per gCell 8.79 on layer (3) METAL3 Average number of tracks per gCell 7.85 on layer (4) METAL4 Average number of tracks per gCell 8.07 on layer (5) METAL5 Average number of tracks per gCell 5.46 on layer (6) METAL6 Number of gCells = 14274 Current Stage stats: [End of Build Congestion map] Elapsed real time: 0:00:00 [End of Build Congestion map] Elapsed cpu time: sys=0:00:00 usr=0:00:00 total=0:00:00 [End of Build Congestion map] Stage (MB): Used 0 Alloctr 0 Proc 0 [End of Build Congestion map] Total (MB): Used 9 Alloctr 10 Proc 417 Total stats: [End of Build Data] Elapsed real time: 0:00:00 [End of Build Data] Elapsed cpu time: sys=0:00:00 usr=0:00:00 total=0:00:00 [End of Build Data] Stage (MB): Used 0 Alloctr 0 Proc 0 [End of Build Data] Total (MB): Used 9 Alloctr 10 Proc 417 Routing whole chip with 1 threads Start GR phase 0 Current Stage stats: [End of Initial Routing] Elapsed real time: 0:00:00 [End of Initial Routing] Elapsed cpu time: sys=0:00:00 usr=0:00:00 total=0:00:00 [End of Initial Routing] Stage (MB): Used 1 Alloctr 1 Proc 1 [End of Initial Routing] Total (MB): Used 10 Alloctr 11 Proc 418 Initial. Routing result: Initial. Both Dirs: Overflow = 592 Max = 4 GRCs = 494 (9.96%) Initial. H routing: Overflow = 457 Max = 4 (GRCs = 5) GRCs = 321 (12.94%) Initial. V routing: Overflow = 135 Max = 3 (GRCs = 1) GRCs = 173 (6.98%) Initial. METAL1 Overflow = 0 Max = 0 (GRCs = 0) GRCs = 0 (0.00%) Initial. METAL2 Overflow = 126 Max = 3 (GRCs = 1) GRCs = 164 (6.61%) Initial. METAL3 Overflow = 457 Max = 4 (GRCs = 5) GRCs = 321 (12.94%) Initial. METAL4 Overflow = 9 Max = 1 (GRCs = 9) GRCs = 9 (0.36%) Initial. METAL5 Overflow = 0 Max = 0 (GRCs = 0) GRCs = 0 (0.00%) Initial. METAL6 Overflow = 0 Max = 0 (GRCs = 0) GRCs = 0 (0.00%) Density distribution: Layer 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 > 1.2 METAL1 100. 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 METAL2 4.29 2.35 4.79 7.90 4.54 16.5 15.4 16.1 18.2 0.08 7.23 1.51 0.71 0.21 METAL3 3.99 1.64 2.65 4.04 5.59 10.2 9.63 13.9 17.2 0.00 18.3 7.06 3.70 1.98 METAL4 11.5 18.4 15.8 11.9 5.84 13.1 8.66 6.35 6.01 0.08 1.81 0.29 0.08 0.00 METAL5 100. 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 METAL6 100. 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 Total 48.8 4.09 4.25 4.36 2.92 7.30 6.16 6.64 7.58 0.03 5.00 1.62 0.82 0.40 Initial. Total Wire Length = 107581.44 Initial. Layer METAL1 wire length = 13.10 Initial. Layer METAL2 wire length = 26553.11 Initial. Layer METAL3 wire length = 52671.72 Initial. Layer METAL4 wire length = 28343.52 Initial. Layer METAL5 wire length = 0.00 Initial. Layer METAL6 wire length = 0.00 Initial. Total Number of Contacts = 16882 Initial. Via via1 count = 8523 Initial. Via via2 count = 6484 Initial. Via via3 count = 1875 Initial. Via via4 count = 0 Initial. Via via5 count = 0 Initial. completed. Start GR phase 1 Current Stage stats: [End of Phase1 Routing] Elapsed real time: 0:00:00 [End of Phase1 Routing] Elapsed cpu time: sys=0:00:00 usr=0:00:00 total=0:00:00 [End of Phase1 Routing] Stage (MB): Used 0 Alloctr 0 Proc 0 [End of Phase1 Routing] Total (MB): Used 10 Alloctr 11 Proc 418 phase1. Routing result: phase1. Both Dirs: Overflow = 177 Max = 3 GRCs = 196 (3.95%) phase1. H routing: Overflow = 76 Max = 3 (GRCs = 1) GRCs = 71 (2.86%) phase1. V routing: Overflow = 101 Max = 3 (GRCs = 3) GRCs = 125 (5.04%) phase1. METAL1 Overflow = 0 Max = 0 (GRCs = 0) GRCs = 0 (0.00%) phase1. METAL2 Overflow = 101 Max = 3 (GRCs = 3) GRCs = 125 (5.04%) phase1. METAL3 Overflow = 76 Max = 3 (GRCs = 1) GRCs = 71 (2.86%) phase1. METAL4 Overflow = 0 Max = 0 (GRCs = 0) GRCs = 0 (0.00%) phase1. METAL5 Overflow = 0 Max = 0 (GRCs = 0) GRCs = 0 (0.00%) phase1. METAL6 Overflow = 0 Max = 0 (GRCs = 0) GRCs = 0 (0.00%) Density distribution: Layer 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 > 1.2 METAL1 100. 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 METAL2 4.16 1.98 5.17 7.15 4.50 16.9 14.8 16.2 20.4 0.25 6.31 0.84 0.76 0.34 METAL3 3.57 1.35 2.69 3.61 4.79 9.42 8.36 12.3 23.1 0.00 28.1 2.31 0.08 0.17 METAL4 10.0 14.1 13.2 10.2 6.09 13.9 10.8 9.29 8.91 0.21 3.03 0.00 0.00 0.00 METAL5 100. 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 METAL6 100. 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 Total 52.9 2.91 3.52 3.50 2.56 6.71 5.67 6.31 8.76 0.08 6.25 0.53 0.14 0.08 phase1. Total Wire Length = 109775.59 phase1. Layer METAL1 wire length = 0.00 phase1. Layer METAL2 wire length = 25423.38 phase1. Layer METAL3 wire length = 51867.28 phase1. Layer METAL4 wire length = 32484.92 phase1. Layer METAL5 wire length = 0.00 phase1. Layer METAL6 wire length = 0.00 phase1. Total Number of Contacts = 17168 phase1. Via via1 count = 8547 phase1. Via via2 count = 6404 phase1. Via via3 count = 2217 phase1. Via via4 count = 0 phase1. Via via5 count = 0 phase1. completed. Start GR phase 2 Current Stage stats: [End of Phase2 Routing] Elapsed real time: 0:00:00 [End of Phase2 Routing] Elapsed cpu time: sys=0:00:00 usr=0:00:00 total=0:00:00 [End of Phase2 Routing] Stage (MB): Used 0 Alloctr 0 Proc 0 [End of Phase2 Routing] Total (MB): Used 10 Alloctr 11 Proc 418 phase2. Routing result: phase2. Both Dirs: Overflow = 92 Max = 2 GRCs = 118 (2.38%) phase2. H routing: Overflow = 48 Max = 2 (GRCs = 3) GRCs = 46 (1.85%) phase2. V routing: Overflow = 43 Max = 2 (GRCs = 2) GRCs = 72 (2.90%) phase2. METAL1 Overflow = 0 Max = 0 (GRCs = 0) GRCs = 0 (0.00%) phase2. METAL2 Overflow = 43 Max = 2 (GRCs = 2) GRCs = 72 (2.90%) phase2. METAL3 Overflow = 48 Max = 2 (GRCs = 3) GRCs = 46 (1.85%) phase2. METAL4 Overflow = 0 Max = 0 (GRCs = 0) GRCs = 0 (0.00%) phase2. METAL5 Overflow = 0 Max = 0 (GRCs = 0) GRCs = 0 (0.00%) phase2. METAL6 Overflow = 0 Max = 0 (GRCs = 0) GRCs = 0 (0.00%) Density distribution: Layer 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 > 1.2 METAL1 100. 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 METAL2 4.20 1.89 5.55 7.99 5.17 19.2 17.0 16.9 16.8 0.13 4.37 0.25 0.29 0.08 METAL3 3.53 1.39 2.65 3.61 4.75 9.29 8.03 12.1 22.3 0.00 30.3 1.64 0.25 0.00 METAL4 10.3 14.6 13.3 10.3 5.84 13.1 11.5 9.25 8.41 0.21 2.98 0.00 0.00 0.00 METAL5 100. 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 METAL6 100. 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 Total 53.0 2.99 3.59 3.66 2.63 6.94 6.09 6.40 7.93 0.06 6.28 0.32 0.09 0.01 phase2. Total Wire Length = 110501.98 phase2. Layer METAL1 wire length = 0.00 phase2. Layer METAL2 wire length = 26359.51 phase2. Layer METAL3 wire length = 51766.35 phase2. Layer METAL4 wire length = 32376.12 phase2. Layer METAL5 wire length = 0.00 phase2. Layer METAL6 wire length = 0.00 phase2. Total Number of Contacts = 17153 phase2. Via via1 count = 8551 phase2. Via via2 count = 6404 phase2. Via via3 count = 2198 phase2. Via via4 count = 0 phase2. Via via5 count = 0 phase2. completed. Start GR phase 3 Current Stage stats: [End of Phase3 Routing] Elapsed real time: 0:00:00 [End of Phase3 Routing] Elapsed cpu time: sys=0:00:00 usr=0:00:00 total=0:00:00 [End of Phase3 Routing] Stage (MB): Used 0 Alloctr 0 Proc 0 [End of Phase3 Routing] Total (MB): Used 10 Alloctr 11 Proc 418 phase3. Routing result: phase3. Both Dirs: Overflow = 87 Max = 3 GRCs = 114 (2.30%) phase3. H routing: Overflow = 45 Max = 2 (GRCs = 1) GRCs = 44 (1.77%) phase3. V routing: Overflow = 41 Max = 3 (GRCs = 1) GRCs = 70 (2.82%) phase3. METAL1 Overflow = 0 Max = 0 (GRCs = 0) GRCs = 0 (0.00%) phase3. METAL2 Overflow = 41 Max = 3 (GRCs = 1) GRCs = 70 (2.82%) phase3. METAL3 Overflow = 45 Max = 2 (GRCs = 1) GRCs = 44 (1.77%) phase3. METAL4 Overflow = 0 Max = 0 (GRCs = 0) GRCs = 0 (0.00%) phase3. METAL5 Overflow = 0 Max = 0 (GRCs = 0) GRCs = 0 (0.00%) phase3. METAL6 Overflow = 0 Max = 0 (GRCs = 0) GRCs = 0 (0.00%) Density distribution: Layer 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 > 1.2 METAL1 100. 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 METAL2 4.16 1.93 5.25 7.94 5.21 19.5 16.9 17.2 16.6 0.13 4.41 0.13 0.42 0.04 METAL3 3.53 1.39 2.56 3.45 4.88 9.04 8.07 12.4 20.6 0.00 32.0 1.64 0.21 0.00 METAL4 10.3 14.2 13.2 10.4 5.72 13.4 10.3 9.50 9.21 0.21 3.36 0.00 0.00 0.00 METAL5 100. 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 METAL6 100. 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 Total 53.0 2.93 3.51 3.64 2.63 7.01 5.88 6.54 7.75 0.06 6.64 0.29 0.11 0.01 phase3. Total Wire Length = 110864.33 phase3. Layer METAL1 wire length = 0.00 phase3. Layer METAL2 wire length = 26536.28 phase3. Layer METAL3 wire length = 51751.66 phase3. Layer METAL4 wire length = 32576.38 phase3. Layer METAL5 wire length = 0.00 phase3. Layer METAL6 wire length = 0.00 phase3. Total Number of Contacts = 17167 phase3. Via via1 count = 8553 phase3. Via via2 count = 6403 phase3. Via via3 count = 2211 phase3. Via via4 count = 0 phase3. Via via5 count = 0 phase3. completed. [End of Whole Chip Routing] Elapsed real time: 0:00:01 [End of Whole Chip Routing] Elapsed cpu time: sys=0:00:00 usr=0:00:01 total=0:00:01 [End of Whole Chip Routing] Stage (MB): Used 1 Alloctr 1 Proc 1 [End of Whole Chip Routing] Total (MB): Used 10 Alloctr 11 Proc 418 Congestion utilization per direction: Average vertical track utilization = 51.63 % Peak vertical track utilization = 108.33 % Average horizontal track utilization = 77.78 % Peak horizontal track utilization = 125.00 % Current Stage stats: [GR: Done] Elapsed real time: 0:00:00 [GR: Done] Elapsed cpu time: sys=0:00:00 usr=0:00:00 total=0:00:00 [GR: Done] Stage (MB): Used 0 Alloctr 0 Proc 0 [GR: Done] Total (MB): Used 10 Alloctr 11 Proc 418 GR Total stats: [GR: Done] Elapsed real time: 0:00:02 [GR: Done] Elapsed cpu time: sys=0:00:00 usr=0:00:01 total=0:00:01 [GR: Done] Stage (MB): Used 2 Alloctr 2 Proc 1 [GR: Done] Total (MB): Used 10 Alloctr 11 Proc 418 Updating congestion ... Final total stats: [End of Global Routing] Elapsed real time: 0:00:02 [End of Global Routing] Elapsed cpu time: sys=0:00:00 usr=0:00:02 total=0:00:02 [End of Global Routing] Stage (MB): Used 1 Alloctr 1 Proc 1 [End of Global Routing] Total (MB): Used 10 Alloctr 10 Proc 418 Start track assignment Printing options for 'set_route_zrt_common_options' Printing options for 'set_route_zrt_track_options' -timing_driven : true Using 1 threads [Track Assign: Read routes] Elapsed real time: 0:00:00 [Track Assign: Read routes] Elapsed cpu time: sys=0:00:00 usr=0:00:00 total=0:00:00 [Track Assign: Read routes] Stage (MB): Used 0 Alloctr 0 Proc 0 [Track Assign: Read routes] Total (MB): Used 10 Alloctr 11 Proc 418 Start initial assignment Assign Horizontal partitions, iteration 0 Routed partition 1/11 Routed partition 2/11 Routed partition 3/11 Routed partition 4/11 Routed partition 5/11 Routed partition 6/11 Routed partition 7/11 Routed partition 8/11 Routed partition 9/11 Routed partition 10/11 Routed partition 11/11 Assign Vertical partitions, iteration 0 Routed partition 1/13 Routed partition 2/13 Routed partition 3/13 Routed partition 4/13 Routed partition 5/13 Routed partition 6/13 Routed partition 7/13 Routed partition 8/13 Routed partition 9/13 Routed partition 10/13 Routed partition 11/13 Routed partition 12/13 Routed partition 13/13 Number of wires with overlap after iteration 0 = 14240 of 23766 [Track Assign: Iteration 0] Elapsed real time: 0:00:01 [Track Assign: Iteration 0] Elapsed cpu time: sys=0:00:00 usr=0:00:01 total=0:00:01 [Track Assign: Iteration 0] Stage (MB): Used 1 Alloctr 1 Proc 9 [Track Assign: Iteration 0] Total (MB): Used 11 Alloctr 12 Proc 428 Reroute to fix overlaps Assign Horizontal partitions, iteration 1 Routed partition 1/11 Routed partition 2/11 Routed partition 3/11 Routed partition 4/11 Routed partition 5/11 Routed partition 6/11 Routed partition 7/11 Routed partition 8/11 Routed partition 9/11 Routed partition 10/11 Routed partition 11/11 Assign Vertical partitions, iteration 1 Routed partition 1/13 Routed partition 2/13 Routed partition 3/13 Routed partition 4/13 Routed partition 5/13 Routed partition 6/13 Routed partition 7/13 Routed partition 8/13 Routed partition 9/13 Routed partition 10/13 Routed partition 11/13 Routed partition 12/13 Routed partition 13/13 [Track Assign: Iteration 1] Elapsed real time: 0:00:02 [Track Assign: Iteration 1] Elapsed cpu time: sys=0:00:00 usr=0:00:02 total=0:00:02 [Track Assign: Iteration 1] Stage (MB): Used 1 Alloctr 1 Proc 9 [Track Assign: Iteration 1] Total (MB): Used 11 Alloctr 12 Proc 428 Number of wires with overlap after iteration 1 = 9156 of 19219 Wire length and via report: --------------------------- Number of metal1 wires: 1023 via01: 0 Number of metal2 wires: 9659 via12: 9635 Number of metal3 wires: 7025 via23: 9379 Number of metal4 wires: 1512 via34: 2409 Number of metal5 wires: 0 via45: 0 Number of metal6 wires: 0 via56: 0 Total number of wires: 19219 vias: 21423 Total metal1 wire length: 796.2 Total metal2 wire length: 30525.6 Total metal3 wire length: 55255.7 Total metal4 wire length: 31273.5 Total metal5 wire length: 0.0 Total metal6 wire length: 0.0 Total wire length: 117851.0 Longest metal1 wire length: 3.2 Longest metal2 wire length: 65.0 Longest metal3 wire length: 153.8 Longest metal4 wire length: 170.8 Longest metal5 wire length: 0.0 Longest metal6 wire length: 0.0 [Track Assign: Done] Elapsed real time: 0:00:03 [Track Assign: Done] Elapsed cpu time: sys=0:00:00 usr=0:00:03 total=0:00:03 [Track Assign: Done] Stage (MB): Used 0 Alloctr 0 Proc 9 [Track Assign: Done] Total (MB): Used 10 Alloctr 11 Proc 428 Printing options for 'set_route_zrt_common_options' Printing options for 'set_route_zrt_detail_options' -save_after_iterations : {1 } -save_cell_prefix : or1200_alu_INIT_RT -timing_driven : true [Dr init] Elapsed real time: 0:00:00 [Dr init] Elapsed cpu time: sys=0:00:00 usr=0:00:00 total=0:00:00 [Dr init] Stage (MB): Used 0 Alloctr 0 Proc 0 [Dr init] Total (MB): Used 10 Alloctr 11 Proc 428 Total number of nets = 2998, of which 0 are not extracted Total number of open nets = 0, of which 0 are frozen Using 1 threads Start DR iteration 0: uniform partition Routed 1/24 Partitions, Violations = 13 Routed 2/24 Partitions, Violations = 29 Routed 3/24 Partitions, Violations = 43 Routed 4/24 Partitions, Violations = 38 Routed 5/24 Partitions, Violations = 29 Routed 6/24 Partitions, Violations = 36 Routed 7/24 Partitions, Violations = 32 Routed 8/24 Partitions, Violations = 28 Routed 9/24 Partitions, Violations = 55 Routed 10/24 Partitions, Violations = 57 Routed 11/24 Partitions, Violations = 51 Routed 12/24 Partitions, Violations = 38 Routed 13/24 Partitions, Violations = 43 Routed 14/24 Partitions, Violations = 44 Routed 15/24 Partitions, Violations = 42 Routed 16/24 Partitions, Violations = 34 Routed 17/24 Partitions, Violations = 36 Routed 18/24 Partitions, Violations = 35 Routed 19/24 Partitions, Violations = 18 Routed 20/24 Partitions, Violations = 13 Routed 21/24 Partitions, Violations = 26 Routed 22/24 Partitions, Violations = 16 Routed 23/24 Partitions, Violations = 3 Routed 24/24 Partitions, Violations = 3 DRC-SUMMARY: @@@@@@@ TOTAL VIOLATIONS = 3 Short : 3 [Iter 0] Elapsed real time: 0:00:08 [Iter 0] Elapsed cpu time: sys=0:00:00 usr=0:00:07 total=0:00:07 [Iter 0] Stage (MB): Used 0 Alloctr 0 Proc 6 [Iter 0] Total (MB): Used 11 Alloctr 12 Proc 435 End DR iteration 0 with 24 parts Start DR iteration 1: non-uniform partition Routed 1/1 Partitions, Violations = 0 DRC-SUMMARY: @@@@@@@ TOTAL VIOLATIONS = 0 [Iter 1] Elapsed real time: 0:00:08 [Iter 1] Elapsed cpu time: sys=0:00:00 usr=0:00:08 total=0:00:08 [Iter 1] Stage (MB): Used 0 Alloctr 0 Proc 6 [Iter 1] Total (MB): Used 11 Alloctr 12 Proc 435 End DR iteration 1 with 1 parts Updating the database ... Saving cell or1200_alu.CEL;1 as or1200_alu_INIT_RT_itr1. or1200_alu_INIT_RT_itr1 saved successfully. Finish DR since reached 0 DRC [DR] Elapsed real time: 0:00:08 [DR] Elapsed cpu time: sys=0:00:00 usr=0:00:08 total=0:00:08 [DR] Stage (MB): Used 0 Alloctr 0 Proc 6 [DR] Total (MB): Used 10 Alloctr 11 Proc 435 [DR: Done] Elapsed real time: 0:00:08 [DR: Done] Elapsed cpu time: sys=0:00:00 usr=0:00:08 total=0:00:08 [DR: Done] Stage (MB): Used 0 Alloctr 0 Proc 6 [DR: Done] Total (MB): Used 10 Alloctr 11 Proc 435 DR finished with 0 open nets, of which 0 are frozen DR finished with 0 violations DRC-SUMMARY: @@@@@@@ TOTAL VIOLATIONS = 0 Total Wire Length = 117636 micron Total Number of Contacts = 21109 Total Number of Wires = 19921 Total Number of PtConns = 2229 Layer METAL1 : 715 micron Layer METAL2 : 29462 micron Layer METAL3 : 54734 micron Layer METAL4 : 32724 micron Layer METAL5 : 0 micron Layer METAL6 : 0 micron Via via3 : 2735 Via via3(rot) : 1 Via via2 : 9127 Via via1 : 6017 Via via1(rot) : 3229 Redundant via conversion report: -------------------------------- Total optimized via conversion rate = 0.00% (0 / 21109 vias) Layer VIA12 = 0.00% (0 / 9246 vias) Un-optimized = 100.00% (9246 vias) Layer VIA23 = 0.00% (0 / 9127 vias) Un-optimized = 100.00% (9127 vias) Layer VIA34 = 0.00% (0 / 2736 vias) Un-optimized = 100.00% (2736 vias) Total double via conversion rate = 0.00% (0 / 21109 vias) Layer VIA12 = 0.00% (0 / 9246 vias) Layer VIA23 = 0.00% (0 / 9127 vias) Layer VIA34 = 0.00% (0 / 2736 vias) Total number of nets = 2998 0 open nets, of which 0 are frozen Total number of excluded ports = 0 ports of 0 unplaced cells connected to 0 nets 0 ports without pins of 0 cells connected to 0 nets 0 ports of 0 cover cells connected to 0 non-pg nets Total number of DRCs = 0 Total number of antenna violations = antenna checking not active Total number of voltage-area violations = no voltage-areas defined Updating the database ... Information: RC extraction has been freed. (PSYN-503) ROPT: Initial Route Done Tue Nov 2 10:31:14 2010 Loading design 'or1200_alu' Information: Library Manufacturing Grid(GridResolution) : 5 Information: Time Unit from Milkyway design library: 'ns' Information: Design Library and main library timing units are matched - 1.000 ns. Information: Resistance Unit from Milkyway design library: 'kohm' Information: Design Library and main library resistance units are matched - 1.000 kohm. Information: Capacitance Unit from Milkyway design library: 'pf' Information: Design Library and main library capacitance units are matched - 1.000 pf. Warning: Inconsistent library data found for layer POLY1. (RCEX-018) Information: Layer METAL1 is ignored for resistance and capacitance computation. (RCEX-019) Information: Layer METAL5 is ignored for resistance and capacitance computation. (RCEX-019) Information: Layer METAL6 is ignored for resistance and capacitance computation. (RCEX-019) Information: The distance unit in Capacitance and Resistance is 1 micron. (RCEX-007) Information: The RC model used is detail route TLU+. (RCEX-015) Information: Start mixed mode parasitic extraction. (RCEX-023) Information: Start rc extraction... Information: Parasitic source is LPE. (RCEX-040) Information: Parasitic mode is RealRC. (RCEX-041) Information: Using virtual shield extraction. (RCEX-081) Information: Extraction mode is MAX. (RCEX-042) Information: Extraction derate is 25/25/25. (RCEX-043) Information: Coupling capacitances are lumped to ground. (RCEX-044) Information: Start back annotation for parasitic extraction. (RCEX-023) Information: End back annotation for parasitic extraction. (RCEX-023) Information: Start timing update for parasitic extraction. (RCEX-023) Information: End timing update for parasitic extraction. (RCEX-023) Information: End parasitic extraction. (RCEX-023) Information: Updating graph... (UID-83) Information: Updating design information... (UID-85) **************************************** Report : qor Design : or1200_alu Version: D-2010.03-ICC-SP1 Date : Tue Nov 2 10:31:19 2010 **************************************** Timing Path Group 'default' ----------------------------------- Levels of Logic: 11.00 Critical Path Length: 1.31 Critical Path Slack: -0.12 Critical Path Clk Period: Undef Total Negative Slack: -2.77 No. of Violating Paths: 34.00 Worst Hold Violation: 0.00 Total Hold Violation: 0.00 No. of Hold Violations: 0.00 ----------------------------------- Cell Count ----------------------------------- Hierarchical Cell Count: 0 Hierarchical Port Count: 0 Leaf Cell Count: 2876 Buf/Inv Cell Count: 655 CT Buf/Inv Cell Count: 0 ----------------------------------- Area ----------------------------------- Combinational Area: 56449.008141 Noncombinational Area: 0.000000 Net Area: 0.000000 Net XLength : 57078.16 Net YLength : 61370.75 ----------------------------------- Cell Area: 56449.008141 Design Area: 56449.008141 Net Length : 118448.91 Design Rules ----------------------------------- Total Number of Nets: 2996 Nets With Violations: 0 ----------------------------------- Hostname: soc2.ece.utexas.edu Compile CPU Statistics ----------------------------------- Resource Sharing: 0.00 Logic Optimization: 0.00 Mapping Optimization: 246.28 ----------------------------------- Overall Compile Time: 246.58 ROPT: (SETUP) WNS: 0.1222 TNS: 2.7689 Number of Violating Path: 34 ROPT: (HOLD) WNS: 0.0000 TNS: 0.0000 Number of Violating Path: 0 ROPT: Number of DRC Violating Nets: 0 ROPT: Number of Route Violation: 0 ROPT: Running Optimization Stage 1 Tue Nov 2 10:31:19 2010 Timing, DRC and Routing Optimization (auto Stage 1) ------------------------------------------------ Loading design 'or1200_alu' Information: Library Manufacturing Grid(GridResolution) : 5 Information: Time Unit from Milkyway design library: 'ns' Information: Design Library and main library timing units are matched - 1.000 ns. Information: Resistance Unit from Milkyway design library: 'kohm' Information: Design Library and main library resistance units are matched - 1.000 kohm. Information: Capacitance Unit from Milkyway design library: 'pf' Information: Design Library and main library capacitance units are matched - 1.000 pf. WNS: 0.12 TNS: 2.77 Number of Violating Paths: 34 Nets with DRC Violations: 0 Total moveable cell area: 56449.3 Total fixed cell area: 0.0 Core area: (1000 1000 200980 298360) Beginning On-Route Optimization -------------------------------- Crosstalk fixing is OFF . Delta-delay: OFF, Delta-Slew: OFF, Static-Noise: OFF. Beginning Timing Optimization ------------------------------ ELAPSED WORST NEG TOTAL NEG DESIGN TIME AREA SLACK SLACK RULE COST ENDPOINT --------- --------- --------- --------- --------- ------------------------- 0:00:01 56452.3 0.12 27.9 0.0 0:00:01 56452.3 0.12 27.9 0.0 0:00:01 56452.3 0.12 27.9 0.0 0:00:01 56455.7 0.12 27.9 0.0 0:00:01 56445.7 0.12 27.9 0.0 0:00:01 56445.7 0.12 27.9 0.0 0:00:02 56439.0 0.12 27.9 0.0 0:00:02 56439.0 0.12 27.9 0.0 0:00:02 56439.0 0.12 27.9 0.0 0:00:02 56439.0 0.12 27.9 0.0 0:00:02 56445.7 0.12 27.9 0.0 0:00:02 56459.0 0.12 27.9 0.0 0:00:02 56459.0 0.12 27.9 0.0 0:00:02 56459.0 0.12 27.8 0.0 0:00:02 56459.0 0.12 27.6 0.0 0:00:02 56472.3 0.12 27.6 0.0 0:00:02 56472.3 0.12 27.6 0.0 0:00:02 56478.9 0.12 27.5 0.0 0:00:02 56478.9 0.12 27.5 0.0 0:00:02 56462.3 0.12 27.5 0.0 0:00:02 56462.3 0.12 27.5 0.0 0:00:02 56465.6 0.12 27.5 0.0 0:00:02 56465.6 0.12 27.5 0.0 0:00:02 56465.6 0.12 27.5 0.0 0:00:02 56459.0 0.12 27.5 0.0 0:00:02 56462.3 0.12 27.5 0.0 0:00:02 56462.3 0.12 27.5 0.0 0:00:02 56465.6 0.12 27.5 0.0 0:00:02 56472.3 0.12 27.4 0.0 0:00:02 56472.3 0.12 27.4 0.0 0:00:03 56478.9 0.12 27.4 0.0 0:00:03 56469.0 0.12 27.3 0.0 0:00:03 56469.0 0.12 27.3 0.0 0:00:03 56462.3 0.12 27.3 0.0 0:00:03 56462.3 0.12 27.3 0.0 0:00:03 56465.6 0.12 27.3 0.0 0:00:03 56465.6 0.12 27.3 0.0 0:00:03 56465.6 0.12 27.2 0.0 0:00:03 56465.6 0.12 27.2 0.0 0:00:03 56475.6 0.12 27.2 0.0 0:00:03 56475.6 0.12 27.2 0.0 0:00:03 56482.3 0.12 27.1 0.0 0:00:03 56482.3 0.12 27.1 0.0 0:00:03 56482.3 0.12 27.1 0.0 0:00:03 56485.6 0.12 27.1 0.0 ELAPSED WORST NEG TOTAL NEG DESIGN TIME AREA SLACK SLACK RULE COST ENDPOINT --------- --------- --------- --------- --------- ------------------------- 0:00:03 56485.6 0.12 27.1 0.0 result[0] 0:00:04 56485.6 0.12 27.1 0.0 result[3] Beginning Phase 1 Design Rule Fixing ------------------------------------ Beginning Post-DRC Delay Recovery ---------------------------------- Optimization Complete --------------------- [begin initializing data for legality checker] Initializing Data Structure ... Reading technology information ... Technology table contains 6 routable metal layers Top most routable layer is set to be metal4 This is considered as a 4-metal-layer design Reading library information from DB ... Reading misc information ... array has 0 vertical and 59 horizontal rows GRC ref loc X corrected GRC ref loc Y corrected 26 pre-routes for placement blockage/checking 986 pre-routes for map congestion calculation Checking information read in ... design style = Horizontal masters, Horizontal rows Preprocessing design ... splitting rows by natural obstacles ... [end initializing data for legality checker] **************************************** Report : Chip Summary Design : or1200_alu Version: D-2010.03-ICC-SP1 Date : Tue Nov 2 10:31:24 2010 **************************************** Std cell utilization: 94.99% (16981/(17877-0)) (Non-fixed + Fixed) Std cell utilization: 94.99% (16981/(17877-0)) (Non-fixed only) Chip area: 17877 sites, bbox (1.00 1.00 200.98 298.36) um Std cell area: 16981 sites, (non-fixed:16981 fixed:0) 2876 cells, (non-fixed:2876 fixed:0) Macro cell area: 0 sites 0 cells Placement blockages: 0 sites, (excluding fixed std cells) 0 sites, (include fixed std cells & chimney area) 0 sites, (complete p/g net blockages) Routing blockages: 0 sites, (partial p/g net blockages) 0 sites, (routing blockages and signal pre-route) Lib cell count: 118 Avg. std cell width: 4.96 um Site array: unit (width: 0.66 um, height: 5.04 um, rows: 59) Physical DB scale: 1000 db_unit = 1 um **************************************** Report : pnet options Design : or1200_alu Version: D-2010.03-ICC-SP1 Date : Tue Nov 2 10:31:24 2010 **************************************** -------------------------------------------------------------------- Layer Blockage Min_width Min_height Via_additive Density -------------------------------------------------------------------- METAL1 none --- --- via additive --- METAL2 none --- --- via additive --- METAL3 none --- --- via additive --- METAL4 none --- --- via additive --- METAL5 none --- --- via additive --- METAL6 none --- --- via additive --- Total 30 (out of 2876) illegal cells need to be legalized. Legalizing 30 illegal cells... Starting legalizer. Initial legalization: 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% (0 sec) Optimizations pass 1: 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% (0 sec) Optimizations pass 2: 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% (0 sec) Optimizations pass 3: 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% (0 sec) Legalization complete (0 total sec) **************************************** Report : Legalize Displacement Design : or1200_alu Version: D-2010.03-ICC-SP1 Date : Tue Nov 2 10:31:24 2010 **************************************** avg cell displacement: 0.793 um ( 0.16 row height) max cell displacement: 1.320 um ( 0.26 row height) std deviation: 0.265 um ( 0.05 row height) number of cell moved: 108 cells (out of 2876 cells) Total 0 cells has large displacement (e.g. > 15.120 um or 3 row height) On-Route Optimization Complete ------------------------------ [begin initializing data for legality checker] Initializing Data Structure ... Reading technology information ... Technology table contains 6 routable metal layers Top most routable layer is set to be metal4 This is considered as a 4-metal-layer design Reading library information from DB ... Reading misc information ... array has 0 vertical and 59 horizontal rows GRC ref loc X corrected GRC ref loc Y corrected 26 pre-routes for placement blockage/checking 986 pre-routes for map congestion calculation Checking information read in ... design style = Horizontal masters, Horizontal rows Preprocessing design ... splitting rows by natural obstacles ... [end initializing data for legality checker] Warning: Die area is not integer multiples of min site height (5040), object's width and height(201980,299360). (PSYN-523) Warning: Die area is not integer multiples of min site width (660), object's width and height(201980,299360). (PSYN-523) **************************************************** Check_legality: Report for Fixed Placement Cells Information: Use the -verbose option to get details about the legality violations. (PSYN-054) **************************************************** (fixed placement) Cells Not on Row : 0 (fixed placement) Cell Overlaps : 0 (fixed placement) Cells overlapping blockages : 0 (fixed placement) Orientation Violations : 0 (fixed placement) Site Violations : 0 (fixed placement) Power Strap Violations : 0 ****************************************************** ****************************************************** Check_legality: Report for Non-fixed Placement Cells Information: Use the -verbose option to get details about the legality violations. (PSYN-054) ****************************************************** Number of Cells Not on Row : 0 Number of Cell Overlaps : 0 Number of Cells overlapping blockages : 0 Number of Orientation Violations : 0 Number of Site Violations : 0 Number of Power Strap Violations : 0 ******************************************** Information: Updating database... GART: Updated design time. GART: Transferring timing data to the router.... * Reached RCCALC-011 limit - remainder will be suppressed GART: Done transferring timing data to the router. ROPT: Optimization Stage 1 Done Tue Nov 2 10:31:25 2010 ROPT: Running Stage 1 Eco Route Tue Nov 2 10:31:25 2010 Beginning incremental routing (auto Stage 1) ---------------------------------------------- Turn off antenna since no rule is specified Cell Min-Routing-Layer = METAL2 Cell Max-Routing-Layer = METAL4 [ECO: Extraction] Elapsed real time: 0:00:00 [ECO: Extraction] Elapsed cpu time: sys=0:00:00 usr=0:00:00 total=0:00:00 [ECO: Extraction] Stage (MB): Used 9 Alloctr 9 Proc 0 [ECO: Extraction] Total (MB): Used 9 Alloctr 10 Proc 451 Num of eco nets = 2998 Num of open eco nets = 126 [ECO: Init] Elapsed real time: 0:00:00 [ECO: Init] Elapsed cpu time: sys=0:00:00 usr=0:00:00 total=0:00:00 [ECO: Init] Stage (MB): Used 9 Alloctr 9 Proc 0 [ECO: Init] Total (MB): Used 10 Alloctr 11 Proc 451 Start Global Route ... [Init] Elapsed real time: 0:00:00 [Init] Elapsed cpu time: sys=0:00:00 usr=0:00:00 total=0:00:00 [Init] Stage (MB): Used 0 Alloctr 0 Proc 0 [Init] Total (MB): Used 10 Alloctr 11 Proc 451 Printing options for 'set_route_zrt_common_options' Printing options for 'set_route_zrt_global_options' -timing_driven : true Begin global routing. Constructing data structure ... Design statistics: Design Bounding Box (0.00,0.00,201.98,299.36) Number of routing layers = 6 layer METAL1, dir Hor, min width = 0.23, min space = 0.23 pitch = 0.56 layer METAL2, dir Ver, min width = 0.28, min space = 0.28 pitch = 0.66 layer METAL3, dir Hor, min width = 0.28, min space = 0.28 pitch = 0.56 layer METAL4, dir Ver, min width = 0.28, min space = 0.28 pitch = 0.66 layer METAL5, dir Hor, min width = 0.28, min space = 0.28 pitch = 0.61 layer METAL6, dir Ver, min width = 0.44, min space = 0.46 pitch = 0.95 Current Stage stats: [End of Build Tech Data] Elapsed real time: 0:00:00 [End of Build Tech Data] Elapsed cpu time: sys=0:00:00 usr=0:00:00 total=0:00:00 [End of Build Tech Data] Stage (MB): Used 0 Alloctr 0 Proc 0 [End of Build Tech Data] Total (MB): Used 10 Alloctr 11 Proc 451 Net statistics: Total number of nets = 2998 Number of nets to route = 126 126 nets are partially connected, of which 126 are detail routed and 0 are global routed. 2872 nets are fully connected, of which 2872 are detail routed and 0 are global routed. Current Stage stats: [End of Build All Nets] Elapsed real time: 0:00:00 [End of Build All Nets] Elapsed cpu time: sys=0:00:00 usr=0:00:00 total=0:00:00 [End of Build All Nets] Stage (MB): Used 0 Alloctr 0 Proc 0 [End of Build All Nets] Total (MB): Used 11 Alloctr 11 Proc 451 Average gCell capacity 0.00 on layer (1) METAL1 Average gCell capacity 7.17 on layer (2) METAL2 Average gCell capacity 7.46 on layer (3) METAL3 Average gCell capacity 7.16 on layer (4) METAL4 Average gCell capacity 0.00 on layer (5) METAL5 Average gCell capacity 0.00 on layer (6) METAL6 Average number of tracks per gCell 8.79 on layer (1) METAL1 Average number of tracks per gCell 7.85 on layer (2) METAL2 Average number of tracks per gCell 8.79 on layer (3) METAL3 Average number of tracks per gCell 7.85 on layer (4) METAL4 Average number of tracks per gCell 8.07 on layer (5) METAL5 Average number of tracks per gCell 5.46 on layer (6) METAL6 Number of gCells = 14274 Current Stage stats: [End of Build Congestion map] Elapsed real time: 0:00:00 [End of Build Congestion map] Elapsed cpu time: sys=0:00:00 usr=0:00:00 total=0:00:00 [End of Build Congestion map] Stage (MB): Used 0 Alloctr 0 Proc 0 [End of Build Congestion map] Total (MB): Used 11 Alloctr 12 Proc 451 Total stats: [End of Build Data] Elapsed real time: 0:00:00 [End of Build Data] Elapsed cpu time: sys=0:00:00 usr=0:00:00 total=0:00:00 [End of Build Data] Stage (MB): Used 0 Alloctr 0 Proc 0 [End of Build Data] Total (MB): Used 11 Alloctr 12 Proc 451 Routing whole chip with 1 threads Start GR phase 0 Current Stage stats: [End of Initial Routing] Elapsed real time: 0:00:00 [End of Initial Routing] Elapsed cpu time: sys=0:00:00 usr=0:00:00 total=0:00:00 [End of Initial Routing] Stage (MB): Used 0 Alloctr 0 Proc 0 [End of Initial Routing] Total (MB): Used 11 Alloctr 12 Proc 451 Initial. Routing result: Initial. Both Dirs: Overflow = 298 Max = 3 GRCs = 285 (5.75%) Initial. H routing: Overflow = 282 Max = 3 (GRCs = 1) GRCs = 268 (10.81%) Initial. V routing: Overflow = 15 Max = 2 (GRCs = 1) GRCs = 17 (0.69%) Initial. METAL1 Overflow = 0 Max = 0 (GRCs = 0) GRCs = 0 (0.00%) Initial. METAL2 Overflow = 7 Max = 2 (GRCs = 1) GRCs = 9 (0.36%) Initial. METAL3 Overflow = 282 Max = 3 (GRCs = 1) GRCs = 268 (10.81%) Initial. METAL4 Overflow = 8 Max = 1 (GRCs = 8) GRCs = 8 (0.32%) Initial. METAL5 Overflow = 0 Max = 0 (GRCs = 0) GRCs = 0 (0.00%) Initial. METAL6 Overflow = 0 Max = 0 (GRCs = 0) GRCs = 0 (0.00%) Density distribution: Layer 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 > 1.2 METAL1 100. 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 METAL2 4.88 5.63 11.3 14.3 8.28 23.2 15.3 9.54 5.51 0.00 1.64 0.04 0.04 0.04 METAL3 3.45 1.60 2.44 3.66 4.37 8.28 8.66 13.9 22.7 0.00 21.8 6.18 2.56 0.29 METAL4 9.88 14.0 12.8 9.67 5.72 12.8 10.7 10.4 10.3 0.21 2.98 0.29 0.04 0.00 METAL5 100. 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 METAL6 100. 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 Total 39.1 4.59 5.76 5.99 3.97 9.59 7.52 7.33 8.34 0.05 5.71 1.41 0.57 0.07 Initial. Total Wire Length = 62.65 Initial. Layer METAL1 wire length = 0.00 Initial. Layer METAL2 wire length = 33.43 Initial. Layer METAL3 wire length = 29.22 Initial. Layer METAL4 wire length = 0.00 Initial. Layer METAL5 wire length = 0.00 Initial. Layer METAL6 wire length = 0.00 Initial. Total Number of Contacts = 37 Initial. Via via1 count = 19 Initial. Via via2 count = 18 Initial. Via via3 count = 0 Initial. Via via4 count = 0 Initial. Via via5 count = 0 Initial. completed. Start GR phase 1 Current Stage stats: [End of Phase1 Routing] Elapsed real time: 0:00:00 [End of Phase1 Routing] Elapsed cpu time: sys=0:00:00 usr=0:00:00 total=0:00:00 [End of Phase1 Routing] Stage (MB): Used 0 Alloctr 0 Proc 0 [End of Phase1 Routing] Total (MB): Used 11 Alloctr 12 Proc 451 phase1. Routing result: phase1. Both Dirs: Overflow = 296 Max = 3 GRCs = 283 (5.71%) phase1. H routing: Overflow = 281 Max = 3 (GRCs = 1) GRCs = 266 (10.73%) phase1. V routing: Overflow = 15 Max = 2 (GRCs = 1) GRCs = 17 (0.69%) phase1. METAL1 Overflow = 0 Max = 0 (GRCs = 0) GRCs = 0 (0.00%) phase1. METAL2 Overflow = 7 Max = 2 (GRCs = 1) GRCs = 9 (0.36%) phase1. METAL3 Overflow = 281 Max = 3 (GRCs = 1) GRCs = 266 (10.73%) phase1. METAL4 Overflow = 8 Max = 1 (GRCs = 8) GRCs = 8 (0.32%) phase1. METAL5 Overflow = 0 Max = 0 (GRCs = 0) GRCs = 0 (0.00%) phase1. METAL6 Overflow = 0 Max = 0 (GRCs = 0) GRCs = 0 (0.00%) Density distribution: Layer 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 > 1.2 METAL1 100. 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 METAL2 4.92 5.63 11.5 14.3 8.24 23.2 15.3 9.50 5.51 0.00 1.64 0.04 0.04 0.04 METAL3 3.45 1.60 2.44 3.66 4.41 8.24 8.66 13.9 22.7 0.00 21.8 6.14 2.56 0.29 METAL4 9.88 14.0 12.8 9.67 5.72 12.8 10.7 10.4 10.3 0.21 2.98 0.29 0.04 0.00 METAL5 100. 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 METAL6 100. 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 Total 39.1 4.59 5.79 5.98 3.97 9.57 7.51 7.32 8.34 0.05 5.72 1.40 0.57 0.07 phase1. Total Wire Length = 56.22 phase1. Layer METAL1 wire length = 0.00 phase1. Layer METAL2 wire length = 27.01 phase1. Layer METAL3 wire length = 29.22 phase1. Layer METAL4 wire length = 0.00 phase1. Layer METAL5 wire length = 0.00 phase1. Layer METAL6 wire length = 0.00 phase1. Total Number of Contacts = 38 phase1. Via via1 count = 19 phase1. Via via2 count = 19 phase1. Via via3 count = 0 phase1. Via via4 count = 0 phase1. Via via5 count = 0 phase1. completed. Start GR phase 2 Current Stage stats: [End of Phase2 Routing] Elapsed real time: 0:00:00 [End of Phase2 Routing] Elapsed cpu time: sys=0:00:00 usr=0:00:00 total=0:00:00 [End of Phase2 Routing] Stage (MB): Used 0 Alloctr 0 Proc 0 [End of Phase2 Routing] Total (MB): Used 11 Alloctr 12 Proc 451 phase2. Routing result: phase2. Both Dirs: Overflow = 296 Max = 3 GRCs = 283 (5.71%) phase2. H routing: Overflow = 281 Max = 3 (GRCs = 1) GRCs = 266 (10.73%) phase2. V routing: Overflow = 15 Max = 2 (GRCs = 1) GRCs = 17 (0.69%) phase2. METAL1 Overflow = 0 Max = 0 (GRCs = 0) GRCs = 0 (0.00%) phase2. METAL2 Overflow = 7 Max = 2 (GRCs = 1) GRCs = 9 (0.36%) phase2. METAL3 Overflow = 281 Max = 3 (GRCs = 1) GRCs = 266 (10.73%) phase2. METAL4 Overflow = 8 Max = 1 (GRCs = 8) GRCs = 8 (0.32%) phase2. METAL5 Overflow = 0 Max = 0 (GRCs = 0) GRCs = 0 (0.00%) phase2. METAL6 Overflow = 0 Max = 0 (GRCs = 0) GRCs = 0 (0.00%) Density distribution: Layer 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 > 1.2 METAL1 100. 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 METAL2 4.92 5.63 11.5 14.3 8.24 23.2 15.3 9.50 5.51 0.00 1.64 0.04 0.04 0.04 METAL3 3.45 1.60 2.44 3.66 4.41 8.24 8.66 13.9 22.7 0.00 21.8 6.14 2.56 0.29 METAL4 9.88 14.0 12.8 9.67 5.72 12.8 10.7 10.4 10.3 0.21 2.98 0.29 0.04 0.00 METAL5 100. 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 METAL6 100. 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 Total 39.3 4.57 5.78 5.96 3.96 9.55 7.49 7.30 8.31 0.05 5.71 1.39 0.57 0.07 phase2. Total Wire Length = 56.22 phase2. Layer METAL1 wire length = 0.00 phase2. Layer METAL2 wire length = 27.01 phase2. Layer METAL3 wire length = 29.22 phase2. Layer METAL4 wire length = 0.00 phase2. Layer METAL5 wire length = 0.00 phase2. Layer METAL6 wire length = 0.00 phase2. Total Number of Contacts = 38 phase2. Via via1 count = 19 phase2. Via via2 count = 19 phase2. Via via3 count = 0 phase2. Via via4 count = 0 phase2. Via via5 count = 0 phase2. completed. [End of Whole Chip Routing] Elapsed real time: 0:00:00 [End of Whole Chip Routing] Elapsed cpu time: sys=0:00:00 usr=0:00:00 total=0:00:00 [End of Whole Chip Routing] Stage (MB): Used 0 Alloctr 0 Proc 0 [End of Whole Chip Routing] Total (MB): Used 11 Alloctr 12 Proc 451 Congestion utilization per direction: Average vertical track utilization = 46.88 % Peak vertical track utilization = 120.00 % Average horizontal track utilization = 78.63 % Peak horizontal track utilization = 200.00 % Current Stage stats: [GR: Done] Elapsed real time: 0:00:00 [GR: Done] Elapsed cpu time: sys=0:00:00 usr=0:00:00 total=0:00:00 [GR: Done] Stage (MB): Used 0 Alloctr 0 Proc 0 [GR: Done] Total (MB): Used 11 Alloctr 12 Proc 451 GR Total stats: [GR: Done] Elapsed real time: 0:00:00 [GR: Done] Elapsed cpu time: sys=0:00:00 usr=0:00:00 total=0:00:00 [GR: Done] Stage (MB): Used 1 Alloctr 1 Proc 0 [GR: Done] Total (MB): Used 11 Alloctr 12 Proc 451 Updating congestion ... Final total stats: [End of Global Routing] Elapsed real time: 0:00:00 [End of Global Routing] Elapsed cpu time: sys=0:00:00 usr=0:00:00 total=0:00:00 [End of Global Routing] Stage (MB): Used 0 Alloctr 0 Proc 0 [End of Global Routing] Total (MB): Used 10 Alloctr 11 Proc 451 [ECO: GR] Elapsed real time: 0:00:01 [ECO: GR] Elapsed cpu time: sys=0:00:00 usr=0:00:01 total=0:00:01 [ECO: GR] Stage (MB): Used 10 Alloctr 10 Proc 0 [ECO: GR] Total (MB): Used 10 Alloctr 11 Proc 451 Start track assignment Printing options for 'set_route_zrt_common_options' Printing options for 'set_route_zrt_track_options' -timing_driven : true Using 1 threads [Track Assign: Read routes] Elapsed real time: 0:00:00 [Track Assign: Read routes] Elapsed cpu time: sys=0:00:00 usr=0:00:00 total=0:00:00 [Track Assign: Read routes] Stage (MB): Used 0 Alloctr 0 Proc 0 [Track Assign: Read routes] Total (MB): Used 10 Alloctr 11 Proc 451 Start initial assignment Assign Horizontal partitions, iteration 0 Routed partition 1/11 Routed partition 2/11 Routed partition 3/11 Routed partition 4/11 Routed partition 5/11 Routed partition 6/11 Routed partition 7/11 Routed partition 8/11 Routed partition 9/11 Routed partition 10/11 Routed partition 11/11 Assign Vertical partitions, iteration 0 Routed partition 1/13 Routed partition 2/13 Routed partition 3/13 Routed partition 4/13 Routed partition 5/13 Routed partition 6/13 Routed partition 7/13 Routed partition 8/13 Routed partition 9/13 Routed partition 10/13 Routed partition 11/13 Routed partition 12/13 Routed partition 13/13 Number of wires with overlap after iteration 0 = 278 of 471 [Track Assign: Iteration 0] Elapsed real time: 0:00:00 [Track Assign: Iteration 0] Elapsed cpu time: sys=0:00:00 usr=0:00:00 total=0:00:00 [Track Assign: Iteration 0] Stage (MB): Used 0 Alloctr 0 Proc 0 [Track Assign: Iteration 0] Total (MB): Used 11 Alloctr 12 Proc 451 Reroute to fix overlaps Assign Horizontal partitions, iteration 1 Routed partition 1/11 Routed partition 2/11 Routed partition 3/11 Routed partition 4/11 Routed partition 5/11 Routed partition 6/11 Routed partition 7/11 Routed partition 8/11 Routed partition 9/11 Routed partition 10/11 Routed partition 11/11 Assign Vertical partitions, iteration 1 Routed partition 1/13 Routed partition 2/13 Routed partition 3/13 Routed partition 4/13 Routed partition 5/13 Routed partition 6/13 Routed partition 7/13 Routed partition 8/13 Routed partition 9/13 Routed partition 10/13 Routed partition 11/13 Routed partition 12/13 Routed partition 13/13 [Track Assign: Iteration 1] Elapsed real time: 0:00:01 [Track Assign: Iteration 1] Elapsed cpu time: sys=0:00:00 usr=0:00:01 total=0:00:01 [Track Assign: Iteration 1] Stage (MB): Used 0 Alloctr 0 Proc 0 [Track Assign: Iteration 1] Total (MB): Used 11 Alloctr 12 Proc 451 Number of wires with overlap after iteration 1 = 153 of 322 Wire length and via report: --------------------------- Number of metal1 wires: 118 via01: 0 Number of metal2 wires: 129 via12: 249 Number of metal3 wires: 62 via23: 115 Number of metal4 wires: 13 via34: 22 Number of metal5 wires: 0 via45: 0 Number of metal6 wires: 0 via56: 0 Total number of wires: 322 vias: 386 Total metal1 wire length: 87.5 Total metal2 wire length: 137.0 Total metal3 wire length: 122.0 Total metal4 wire length: 38.2 Total metal5 wire length: 0.0 Total metal6 wire length: 0.0 Total wire length: 384.7 Longest metal1 wire length: 3.2 Longest metal2 wire length: 4.5 Longest metal3 wire length: 4.6 Longest metal4 wire length: 10.6 Longest metal5 wire length: 0.0 Longest metal6 wire length: 0.0 [Track Assign: Done] Elapsed real time: 0:00:01 [Track Assign: Done] Elapsed cpu time: sys=0:00:00 usr=0:00:01 total=0:00:01 [Track Assign: Done] Stage (MB): Used 0 Alloctr 0 Proc 0 [Track Assign: Done] Total (MB): Used 10 Alloctr 11 Proc 451 [ECO: CDR] Elapsed real time: 0:00:02 [ECO: CDR] Elapsed cpu time: sys=0:00:00 usr=0:00:02 total=0:00:02 [ECO: CDR] Stage (MB): Used 10 Alloctr 10 Proc 0 [ECO: CDR] Total (MB): Used 10 Alloctr 11 Proc 451 Printing options for 'set_route_zrt_common_options' Printing options for 'set_route_zrt_detail_options' -timing_driven : true Total number of nets = 2998, of which 0 are not extracted Total number of open nets = 0, of which 0 are frozen Using 1 threads Start DR iteration 0: uniform partition Routed 1/24 Partitions, Violations = 0 Routed 2/24 Partitions, Violations = 0 Routed 3/24 Partitions, Violations = 0 Routed 4/24 Partitions, Violations = 0 Routed 5/24 Partitions, Violations = 0 Routed 6/24 Partitions, Violations = 0 Routed 7/24 Partitions, Violations = 3 Routed 8/24 Partitions, Violations = 3 Routed 9/24 Partitions, Violations = 7 Routed 10/24 Partitions, Violations = 11 Routed 11/24 Partitions, Violations = 8 Routed 12/24 Partitions, Violations = 5 Routed 13/24 Partitions, Violations = 6 Routed 14/24 Partitions, Violations = 11 Routed 15/24 Partitions, Violations = 10 Routed 16/24 Partitions, Violations = 8 Routed 17/24 Partitions, Violations = 3 Routed 18/24 Partitions, Violations = 7 Routed 19/24 Partitions, Violations = 4 Routed 20/24 Partitions, Violations = 4 Routed 21/24 Partitions, Violations = 10 Routed 22/24 Partitions, Violations = 10 Routed 23/24 Partitions, Violations = 0 Routed 24/24 Partitions, Violations = 0 DRC-SUMMARY: @@@@@@@ TOTAL VIOLATIONS = 0 [Iter 0] Elapsed real time: 0:00:03 [Iter 0] Elapsed cpu time: sys=0:00:00 usr=0:00:03 total=0:00:03 [Iter 0] Stage (MB): Used 0 Alloctr 0 Proc 0 [Iter 0] Total (MB): Used 11 Alloctr 12 Proc 451 End DR iteration 0 with 24 parts Finish DR since reached 0 DRC DR finished with 0 violations DRC-SUMMARY: @@@@@@@ TOTAL VIOLATIONS = 0 Total Wire Length = 117764 micron Total Number of Contacts = 21135 Total Number of Wires = 20095 Total Number of PtConns = 2233 Layer METAL1 : 727 micron Layer METAL2 : 29496 micron Layer METAL3 : 54751 micron Layer METAL4 : 32790 micron Layer METAL5 : 0 micron Layer METAL6 : 0 micron Via via3 : 2765 Via via3(rot) : 1 Via via2 : 9131 Via via1 : 6123 Via via1(rot) : 3115 Redundant via conversion report: -------------------------------- Total optimized via conversion rate = 0.00% (0 / 21135 vias) Layer VIA12 = 0.00% (0 / 9238 vias) Un-optimized = 100.00% (9238 vias) Layer VIA23 = 0.00% (0 / 9131 vias) Un-optimized = 100.00% (9131 vias) Layer VIA34 = 0.00% (0 / 2766 vias) Un-optimized = 100.00% (2766 vias) Total double via conversion rate = 0.00% (0 / 21135 vias) Layer VIA12 = 0.00% (0 / 9238 vias) Layer VIA23 = 0.00% (0 / 9131 vias) Layer VIA34 = 0.00% (0 / 2766 vias) Begin timing optimization in DR ... Printing options for 'set_route_zrt_common_options' Printing options for 'set_route_zrt_detail_options' -timing_driven : true [Dr init] Elapsed real time: 0:00:03 [Dr init] Elapsed cpu time: sys=0:00:00 usr=0:00:03 total=0:00:03 [Dr init] Stage (MB): Used 0 Alloctr 0 Proc 0 [Dr init] Total (MB): Used 10 Alloctr 11 Proc 451 Begin timing soft drc check ... Created 301 soft drcs Information: Merged away 34 aligned/redundant DRCs. (ZRT-305) DRC-SUMMARY: @@@@@@@ TOTAL VIOLATIONS = 267 [SOFT DRC] Elapsed real time: 0:00:00 [SOFT DRC] Elapsed cpu time: sys=0:00:00 usr=0:00:00 total=0:00:00 [SOFT DRC] Stage (MB): Used 0 Alloctr 0 Proc 0 [SOFT DRC] Total (MB): Used 10 Alloctr 11 Proc 451 Total number of nets = 2998, of which 0 are not extracted Total number of open nets = 0, of which 0 are frozen Using 1 threads Start DR iteration 0: non-uniform partition Routed 1/9 Partitions, Violations = 0 Routed 2/9 Partitions, Violations = 0 Routed 3/9 Partitions, Violations = 0 Routed 4/9 Partitions, Violations = 0 Routed 5/9 Partitions, Violations = 0 Routed 6/9 Partitions, Violations = 1 Routed 7/9 Partitions, Violations = 1 Routed 8/9 Partitions, Violations = 0 Routed 9/9 Partitions, Violations = 0 DRC-SUMMARY: @@@@@@@ TOTAL VIOLATIONS = 122 Internal Soft Spacing types : 122 [Iter 0] Elapsed real time: 0:00:05 [Iter 0] Elapsed cpu time: sys=0:00:00 usr=0:00:05 total=0:00:05 [Iter 0] Stage (MB): Used 0 Alloctr 0 Proc 0 [Iter 0] Total (MB): Used 11 Alloctr 12 Proc 451 End DR iteration 0 with 9 parts Start DR iteration 1: non-uniform partition DRC-SUMMARY: @@@@@@@ TOTAL VIOLATIONS = 122 Internal Soft Spacing types : 122 [Iter 1] Elapsed real time: 0:00:05 [Iter 1] Elapsed cpu time: sys=0:00:00 usr=0:00:05 total=0:00:05 [Iter 1] Stage (MB): Used 0 Alloctr 0 Proc 0 [Iter 1] Total (MB): Used 11 Alloctr 12 Proc 451 End DR iteration 1 with 0 parts Stop DR since reached max number of iterations [DR] Elapsed real time: 0:00:05 [DR] Elapsed cpu time: sys=0:00:00 usr=0:00:05 total=0:00:05 [DR] Stage (MB): Used 0 Alloctr 0 Proc 0 [DR] Total (MB): Used 10 Alloctr 11 Proc 451 [DR: Done] Elapsed real time: 0:00:05 [DR: Done] Elapsed cpu time: sys=0:00:00 usr=0:00:05 total=0:00:05 [DR: Done] Stage (MB): Used 0 Alloctr 0 Proc 0 [DR: Done] Total (MB): Used 10 Alloctr 11 Proc 451 Finished timing optimization in DR ... Nets that have been modified: Net 1 = n375 Net 2 = n376 Net 3 = n379 Net 4 = n386 Net 5 = n388 Net 6 = n392 Net 7 = n403 Net 8 = n404 Net 9 = n325 Net 10 = n335 Net 11 = n336 Net 12 = n338 Net 13 = n342 Net 14 = n347 Net 15 = n348 Net 16 = n356 Net 17 = n358 Net 18 = n359 Net 19 = n282 Net 20 = n284 Net 21 = n298 Net 22 = n306 Net 23 = n307 Net 24 = n310 Net 25 = n311 Net 26 = n314 Net 27 = n323 Net 28 = n241 Net 29 = n268 Net 30 = n272 Net 31 = n274 Net 32 = n198 Net 33 = n199 Net 34 = n205 Net 35 = n211 Net 36 = n219 Net 37 = n220 Net 38 = n221 Net 39 = n224 Net 40 = n227 Net 41 = n229 Net 42 = n151 Net 43 = n158 Net 44 = n163 Net 45 = n165 Net 46 = n184 Net 47 = n112 Net 48 = n129 Net 49 = n148 Net 50 = n71 Net 51 = n102 Net 52 = sub_x_208_0\/n88 Net 53 = add_x_187_0\/n100 Net 54 = sub_x_208_0\/n70 Net 55 = DP_OP_48_296_6285\/n4 Net 56 = sub_x_208_0\/n61 Net 57 = add_x_187_0\/n44 Net 58 = n2 Net 59 = n3 Net 60 = b[4] Net 61 = n15 Net 62 = b[0] Net 63 = n32 Net 64 = n36 Net 65 = sub_x_208_0\/n45 Net 66 = add_x_187_0\/n49 Net 67 = n413 Net 68 = n420 Net 69 = N626 Net 70 = DP_OP_48_296_6285\/n309 Net 71 = add_x_187_0\/n48 Net 72 = a[26] Net 73 = mult_mac_result[6] Net 74 = DP_OP_48_296_6285\/n109 Net 75 = sub_x_208_0\/n324 Net 76 = sub_x_208_0\/n326 Net 77 = sub_x_208_0\/n320 Net 78 = sub_x_208_0\/n58 Net 79 = add_x_187_0\/n59 Net 80 = a[24] Net 81 = a[25] Net 82 = n424 Net 83 = n1418 Net 84 = n1520 Net 85 = n1251 Net 86 = sub_x_208_0\/n94 Net 87 = sub_x_208_0\/n293 Net 88 = sub_x_208_0\/n291 Net 89 = add_x_187_0\/n118 Net 90 = sub_x_208_0\/n300 Net 91 = DP_OP_48_296_6285\/n311 Net 92 = DP_OP_48_296_6285\/n37 Net 93 = sub_x_208_0\/n50 Net 94 = add_x_187_0\/n301 Net 95 = n427 Net 96 = n429 Net 97 = sub_x_208_0\/n60 Net 98 = sub_x_208_0\/n85 Net 99 = add_x_187_0\/n66 Net 100 = n1130 .... and 327 other nets Number of nets modified = 427 (out of 2998) [DR: Done] Elapsed real time: 0:00:05 [DR: Done] Elapsed cpu time: sys=0:00:00 usr=0:00:05 total=0:00:05 [DR: Done] Stage (MB): Used 0 Alloctr 0 Proc 0 [DR: Done] Total (MB): Used 10 Alloctr 11 Proc 451 [ECO: DR] Elapsed real time: 0:00:08 [ECO: DR] Elapsed cpu time: sys=0:00:00 usr=0:00:07 total=0:00:08 [ECO: DR] Stage (MB): Used 10 Alloctr 10 Proc 0 [ECO: DR] Total (MB): Used 10 Alloctr 11 Proc 451 ECO Route finished with 0 open nets, of which 0 are frozen ECO Route finished with 0 violations DRC-SUMMARY: @@@@@@@ TOTAL VIOLATIONS = 0 Total Wire Length = 117932 micron Total Number of Contacts = 21222 Total Number of Wires = 20361 Total Number of PtConns = 2224 Layer METAL1 : 728 micron Layer METAL2 : 29663 micron Layer METAL3 : 54657 micron Layer METAL4 : 32885 micron Layer METAL5 : 0 micron Layer METAL6 : 0 micron Via via3 : 2809 Via via3(rot) : 1 Via via2 : 9171 Via via1 : 6110 Via via1(rot) : 3131 Redundant via conversion report: -------------------------------- Total optimized via conversion rate = 0.00% (0 / 21222 vias) Layer VIA12 = 0.00% (0 / 9241 vias) Un-optimized = 100.00% (9241 vias) Layer VIA23 = 0.00% (0 / 9171 vias) Un-optimized = 100.00% (9171 vias) Layer VIA34 = 0.00% (0 / 2810 vias) Un-optimized = 100.00% (2810 vias) Total double via conversion rate = 0.00% (0 / 21222 vias) Layer VIA12 = 0.00% (0 / 9241 vias) Layer VIA23 = 0.00% (0 / 9171 vias) Layer VIA34 = 0.00% (0 / 2810 vias) Total number of nets = 2998 0 open nets, of which 0 are frozen Total number of excluded ports = 0 ports of 0 unplaced cells connected to 0 nets 0 ports without pins of 0 cells connected to 0 nets 0 ports of 0 cover cells connected to 0 non-pg nets Total number of DRCs = 0 Total number of antenna violations = antenna checking not active Total number of voltage-area violations = no voltage-areas defined Total Wire Length = 117932 micron Total Number of Contacts = 21222 Total Number of Wires = 20361 Total Number of PtConns = 2224 Layer METAL1 : 728 micron Layer METAL2 : 29663 micron Layer METAL3 : 54657 micron Layer METAL4 : 32885 micron Layer METAL5 : 0 micron Layer METAL6 : 0 micron Via via3 : 2809 Via via3(rot) : 1 Via via2 : 9171 Via via1 : 6110 Via via1(rot) : 3131 Redundant via conversion report: -------------------------------- Total optimized via conversion rate = 0.00% (0 / 21222 vias) Layer VIA12 = 0.00% (0 / 9241 vias) Un-optimized = 100.00% (9241 vias) Layer VIA23 = 0.00% (0 / 9171 vias) Un-optimized = 100.00% (9171 vias) Layer VIA34 = 0.00% (0 / 2810 vias) Un-optimized = 100.00% (2810 vias) Total double via conversion rate = 0.00% (0 / 21222 vias) Layer VIA12 = 0.00% (0 / 9241 vias) Layer VIA23 = 0.00% (0 / 9171 vias) Layer VIA34 = 0.00% (0 / 2810 vias) Updating the database ... ...updated 427 nets [ECO: End] Elapsed real time: 0:00:08 [ECO: End] Elapsed cpu time: sys=0:00:00 usr=0:00:08 total=0:00:08 [ECO: End] Stage (MB): Used 0 Alloctr 0 Proc 0 [ECO: End] Total (MB): Used 0 Alloctr 1 Proc 451 Information: RC extraction has been freed. (PSYN-503) ROPT: Stage 1 Eco Route Done Tue Nov 2 10:31:34 2010 Loading design 'or1200_alu' Information: Library Manufacturing Grid(GridResolution) : 5 Information: Time Unit from Milkyway design library: 'ns' Information: Design Library and main library timing units are matched - 1.000 ns. Information: Resistance Unit from Milkyway design library: 'kohm' Information: Design Library and main library resistance units are matched - 1.000 kohm. Information: Capacitance Unit from Milkyway design library: 'pf' Information: Design Library and main library capacitance units are matched - 1.000 pf. Warning: Inconsistent library data found for layer POLY1. (RCEX-018) Information: Layer METAL1 is ignored for resistance and capacitance computation. (RCEX-019) Information: Layer METAL5 is ignored for resistance and capacitance computation. (RCEX-019) Information: Layer METAL6 is ignored for resistance and capacitance computation. (RCEX-019) Information: The distance unit in Capacitance and Resistance is 1 micron. (RCEX-007) Information: The RC model used is detail route TLU+. (RCEX-015) Information: Start mixed mode parasitic extraction. (RCEX-023) Information: Start rc extraction... Information: Parasitic source is LPE. (RCEX-040) Information: Parasitic mode is RealRC. (RCEX-041) Information: Using virtual shield extraction. (RCEX-081) Information: Extraction mode is MAX. (RCEX-042) Information: Extraction derate is 25/25/25. (RCEX-043) Information: Coupling capacitances are lumped to ground. (RCEX-044) Information: Start back annotation for parasitic extraction. (RCEX-023) Information: End back annotation for parasitic extraction. (RCEX-023) Information: Start timing update for parasitic extraction. (RCEX-023) Information: End timing update for parasitic extraction. (RCEX-023) Information: End parasitic extraction. (RCEX-023) Information: Updating graph... (UID-83) Information: Updating design information... (UID-85) **************************************** Report : qor Design : or1200_alu Version: D-2010.03-ICC-SP1 Date : Tue Nov 2 10:31:38 2010 **************************************** Timing Path Group 'default' ----------------------------------- Levels of Logic: 10.00 Critical Path Length: 0.88 Critical Path Slack: -0.11 Critical Path Clk Period: Undef Total Negative Slack: -2.76 No. of Violating Paths: 34.00 Worst Hold Violation: 0.00 Total Hold Violation: 0.00 No. of Hold Violations: 0.00 ----------------------------------- Cell Count ----------------------------------- Hierarchical Cell Count: 0 Hierarchical Port Count: 0 Leaf Cell Count: 2876 Buf/Inv Cell Count: 655 CT Buf/Inv Cell Count: 0 ----------------------------------- Area ----------------------------------- Combinational Area: 56485.598537 Noncombinational Area: 0.000000 Net Area: 0.000000 Net XLength : 57178.10 Net YLength : 61593.55 ----------------------------------- Cell Area: 56485.598537 Design Area: 56485.598537 Net Length : 118771.65 Design Rules ----------------------------------- Total Number of Nets: 2996 Nets With Violations: 0 ----------------------------------- Hostname: soc2.ece.utexas.edu Compile CPU Statistics ----------------------------------- Resource Sharing: 0.00 Logic Optimization: 0.00 Mapping Optimization: 249.72 ----------------------------------- Overall Compile Time: 250.15 ROPT: (SETUP) WNS: 0.1096 TNS: 2.7573 Number of Violating Path: 34 ROPT: (HOLD) WNS: 0.0000 TNS: 0.0000 Number of Violating Path: 0 ROPT: Number of DRC Violating Nets: 0 ROPT: Number of Route Violation: 0 about to run route_search_repair INFO: CapModel (/scratch/mark/ICC/cpu/blocks/or1200_alu/or1200_alu.mw/lib_2) is attached INFO: ResModel2.2 (/scratch/mark/ICC/cpu/blocks/or1200_alu/or1200_alu.mw/lib_2) is attached INFO: ITF_Combo (/scratch/mark/ICC/cpu/blocks/or1200_alu/or1200_alu.mw/lib_3) is attached ITF to TLU+ conversion successful ! Running router in separate process ... Error: It is not recommended to use classic router commands after Zroute commands. (RT-302) Select via(via5) as the default for layer(VIA56) Select via(via4) as the default for layer(VIA45) Select via(via3) as the default for layer(VIA34) Select via(via2) as the default for layer(VIA23) Select via(via1) as the default for layer(VIA12) Select via(CONT1) as the default for layer(CONT) [via5] and [via4] stacking is allowed [via4] and [via5] stacking is allowed [via4] and [via3] stacking is allowed [via3] and [via4] stacking is allowed [via3] and [via2] stacking is allowed [via2] and [via3] stacking is allowed [via2] and [via1] stacking is allowed [via1] and [via2] stacking is allowed # Masters = 120 , # Instances = 2877 , # Nets = 2998 [via1] and [CONT1] stacking is allowed WARNING: Net [n2288] is broken into 2 parts, reconnect! WARNING: Net [n1939] is broken into 4 parts, reconnect! WARNING: Net [n1349] is broken into 2 parts, reconnect! WARNING: Net [n2563] is broken into 2 parts, reconnect! WARNING: Net [n878] is broken into 2 parts, reconnect! WARNING: Net [alu_op[2]] is broken into 3 parts, reconnect! WARNING: Net [alu_op[3]] is broken into 2 parts, reconnect! WARNING: Net [b[8]] is broken into 3 parts, reconnect! WARNING: Net [sub_x_208_0\/n330] is broken into 2 parts, reconnect! WARNING: Net [b[10]] is broken into 2 parts, reconnect! WARNING: Net [n2311] is broken into 2 parts, reconnect! WARNING: Net [n1765] is broken into 2 parts, reconnect! WARNING: Net [DP_OP_48_296_6285\/n330] is broken into 2 parts, reconnect! WARNING: Net [n2425] is broken into 2 parts, reconnect! WARNING: Net [n1762] is broken into 3 parts, reconnect! WARNING: Net [a[6]] is broken into 7 parts, reconnect! WARNING: Net [n1761] is broken into 2 parts, reconnect! WARNING: Net [n1305] is broken into 5 parts, reconnect! WARNING: Net [DP_OP_48_296_6285\/n202] is broken into 2 parts, reconnect! WARNING: Net [DP_OP_48_296_6285\/n219] is broken into 2 parts, reconnect! WARNING: Net [a[20]] is broken into 4 parts, reconnect! WARNING: Net [n1331] is broken into 3 parts, reconnect! WARNING: Net [DP_OP_48_296_6285\/n397] is broken into 2 parts, reconnect! WARNING: Net [n1807] is broken into 2 parts, reconnect! WARNING: Net [n2388] is broken into 4 parts, reconnect! WARNING: Net [n2386] is broken into 2 parts, reconnect! WARNING: Net [n2131] is broken into 2 parts, reconnect! WARNING: Net [b[2]] is broken into 6 parts, reconnect! WARNING: Net [n1763] is broken into 2 parts, reconnect! WARNING: Net [a[11]] is broken into 2 parts, reconnect! WARNING: Net [add_x_187_0\/n241] is broken into 2 parts, reconnect! WARNING: Net [n795] is broken into 2 parts, reconnect! WARNING: Net [add_x_187_0\/n174] is broken into 2 parts, reconnect! WARNING: Net [a[9]] is broken into 2 parts, reconnect! WARNING: Net [n1100] is broken into 2 parts, reconnect! WARNING: Net [a[12]] is broken into 4 parts, reconnect! WARNING: Net [b[3]] is broken into 2 parts, reconnect! WARNING: Net [a[4]] is broken into 4 parts, reconnect! WARNING: Net [n1777] is broken into 3 parts, reconnect! WARNING: Net [b[22]] is broken into 2 parts, reconnect! WARNING: Net [a[1]] is broken into 5 parts, reconnect! WARNING: Net [sub_x_208_0\/n256] is broken into 2 parts, reconnect! WARNING: Net [n1231] is broken into 2 parts, reconnect! WARNING: Net [n1589] is broken into 2 parts, reconnect! WARNING: Net [n1388] is broken into 2 parts, reconnect! WARNING: Net [b[5]] is broken into 3 parts, reconnect! WARNING: Net [n1308] is broken into 5 parts, reconnect! WARNING: Net [add_x_187_0\/n26] is broken into 2 parts, reconnect! WARNING: Net [n516] is broken into 2 parts, reconnect! WARNING: Net [n1376] is broken into 3 parts, reconnect! WARNING: Net [add_x_187_0\/n226] is broken into 2 parts, reconnect! WARNING: Net [DP_OP_48_296_6285\/n200] is broken into 3 parts, reconnect! WARNING: Net [n1859] is broken into 3 parts, reconnect! WARNING: Net [DP_OP_48_296_6285\/n166] is broken into 3 parts, reconnect! WARNING: Net [add_x_187_0\/n179] is broken into 2 parts, reconnect! WARNING: Net [add_x_187_0\/n164] is broken into 2 parts, reconnect! WARNING: Net [add_x_187_0\/n75] is broken into 2 parts, reconnect! WARNING: Net [n729] is broken into 2 parts, reconnect! WARNING: Net [n495] is broken into 2 parts, reconnect! WARNING: Net [n1310] is broken into 2 parts, reconnect! WARNING: Net [add_x_187_0\/n113] is broken into 2 parts, reconnect! WARNING: Net [n2401] is broken into 2 parts, reconnect! WARNING: Net [sub_x_208_0\/n81] is broken into 2 parts, reconnect! WARNING: Net [sub_x_208_0\/n63] is broken into 3 parts, reconnect! WARNING: Net [n741] is broken into 2 parts, reconnect! WARNING: Net [n581] is broken into 2 parts, reconnect! WARNING: Net [n2093] is broken into 2 parts, reconnect! WARNING: Net [n2011] is broken into 3 parts, reconnect! WARNING: Net [n2457] is broken into 3 parts, reconnect! WARNING: Net [n2415] is broken into 2 parts, reconnect! WARNING: Net [b[21]] is broken into 2 parts, reconnect! WARNING: Net [a[16]] is broken into 7 parts, reconnect! WARNING: Net [n2297] is broken into 2 parts, reconnect! WARNING: Net [add_x_187_0\/n97] is broken into 3 parts, reconnect! WARNING: Net [n2360] is broken into 2 parts, reconnect! WARNING: Net [n469] is broken into 2 parts, reconnect! WARNING: Net [b[31]] is broken into 2 parts, reconnect! WARNING: Net [n1362] is broken into 2 parts, reconnect! WARNING: Net [n2337] is broken into 2 parts, reconnect! WARNING: Net [b[14]] is broken into 3 parts, reconnect! WARNING: Net [n1566] is broken into 2 parts, reconnect! WARNING: Net [n1436] is broken into 3 parts, reconnect! WARNING: Net [n2408] is broken into 2 parts, reconnect! WARNING: Net [n1218] is broken into 2 parts, reconnect! WARNING: Net [n2096] is broken into 2 parts, reconnect! WARNING: Net [n1365] is broken into 2 parts, reconnect! WARNING: Net [cust5_limm[5]] is broken into 4 parts, reconnect! WARNING: Net [n1346] is broken into 3 parts, reconnect! WARNING: Net [n2261] is broken into 2 parts, reconnect! WARNING: Net [sub_x_208_0\/n7] is broken into 2 parts, reconnect! WARNING: Net [n640] is broken into 2 parts, reconnect! WARNING: Net [n1533] is broken into 3 parts, reconnect! WARNING: Net [n971] is broken into 2 parts, reconnect! WARNING: Net [n743] is broken into 2 parts, reconnect! WARNING: Net [a[31]] is broken into 2 parts, reconnect! WARNING: Net [DP_OP_48_296_6285\/n47] is broken into 2 parts, reconnect! WARNING: Net [n432] is broken into 2 parts, reconnect! WARNING: Net [n1213] is broken into 2 parts, reconnect! WARNING: Net [DP_OP_48_296_6285\/n37] is broken into 2 parts, reconnect! WARNING: Net [a[25]] is broken into 2 parts, reconnect! WARNING: Net [DP_OP_48_296_6285\/n230] is broken into 2 parts, reconnect! WARNING: Net [n35] is broken into 3 parts, reconnect! WARNING: Net [n33] is broken into 2 parts, reconnect! WARNING: Net [b[0]] is broken into 4 parts, reconnect! WARNING: Net [sub_x_208_0\/n70] is broken into 3 parts, reconnect! WARNING: Net [n117] is broken into 2 parts, reconnect! WARNING: Net [n178] is broken into 2 parts, reconnect! WARNING: Net [n153] is broken into 6 parts, reconnect! WARNING: Net [n152] is broken into 2 parts, reconnect! WARNING: Net [n151] is broken into 3 parts, reconnect! WARNING: Net [n245] is broken into 2 parts, reconnect! WARNING: Net [n239] is broken into 2 parts, reconnect! WARNING: Net [n321] is broken into 3 parts, reconnect! WARNING: Net [n300] is broken into 2 parts, reconnect! WARNING: Net [n357] is broken into 3 parts, reconnect! WARNING: Net [n352] is broken into 2 parts, reconnect! WARNING: Net [n329] is broken into 2 parts, reconnect! WARNING: Net [n370] is broken into 2 parts, reconnect! There are 118 open signal nets! Re-connect 118 open nets! Reconnect 148 connections! DRC-SUMMARY: @@@@@@@ TOTAL VIOLATIONS = 550 (0) Search-Repair Loop (1 of 5) DRC-SUMMARY: @@@@@@@ TOTAL VIOLATIONS = 0 (0) [ ROUTE] CPU = 0:00:03, Elapsed = 0:00:04 [ ROUTE] Peak Memory = 107M Data = 43M Total Wire Length = 118856 micron Total Number of Contacts = 21222 Layer METAL1 : 732 micron Layer METAL2 : 30366 micron Layer METAL3 : 54816 micron Layer METAL4 : 32943 micron Via via3 : 1 Via via3 : 2818 Via via2 : 9167 Via via1 : 3155 Via via1 : 6081 DRC-SUMMARY: @@@@@@@ TOTAL VIOLATIONS = 0 (0) Updating the database ... [ UPDATE DB] CPU = 0:00:03, Elapsed = 0:00:04 [ UPDATE DB] Peak Memory = 107M Data = 11M Information: RC extraction has been freed. (PSYN-503) inserting filler decap cells VA selected: -->clean up DB before adding filler === Filler Cell Insertion ====== PARAM: respectMacroPadding = FALSE PARAM: respectPlacementBlockage = TRUE Initializing Data Structure ... Reading technology information ... Technology table contains 6 routable metal layers Top most routable layer is set to be metal4 This is considered as a 4-metal-layer design Reading library information from DB ... Reading netlist information from DB ... 2876 placeable cells 0 cover cells 276 IO cells/pins 3152 cell instances Sorting cells, nets, pins ... net pin threshold = 33 Reading misc information ... array has 0 vertical and 59 horizontal rows GRC ref loc X corrected GRC ref loc Y corrected 26 pre-routes for placement blockage/checking 986 pre-routes for map congestion calculation Auto Set : first cut = vertical Checking information read in ... design style = Horizontal masters, Horizontal rows Processing std cells for voltage threshold type... Preprocessing design ... processing macro cells (if any) processing preroute blockages (if any) processing hard placement blockages (if any) processing soft placement blockages (if any) Auto Set : first cut = horizontal processing std cells Pass I: adjust placeable rows Pass II: mark placed cells Processing filler cells... Hierarchical update for new filler cells INFO: Fillers rules in use ... ** LR Filler Rules ** ** VT Filler Rules ** ... max fillers each 100 Filling cell with master and connecting PG nets... The first filler cell name is xofiller!FILL8!1 The last filler cell name is xofiller!FILL8!7 7 filler cells with master were inserted Filling cell with master and connecting PG nets... The first filler cell name is xofiller!FILL4!1 The last filler cell name is xofiller!FILL4!84 84 filler cells with master were inserted Filling cell with master and connecting PG nets... The first filler cell name is xofiller!FILL2!1 The last filler cell name is xofiller!FILL2!153 153 filler cells with master were inserted Filling cell with master and connecting PG nets... The first filler cell name is xofiller!FILL1!1 The last filler cell name is xofiller!FILL1!198 198 filler cells with master were inserted === End of Filler Cell Insertion === -->clean up DB after adding filler Information: PG PORT PUNCHING: Number of ports connected: 884 (MW-337) Information: PG PORT PUNCHING: Total number of changes: 884 (MW-339) Information: Performing CEL netlist consistency check. (MWDC-118) Information: CEL consistency check PASSED. (MWDC-119) Info: Writing NID in 3.0 format Info: Writing NID in 3.0 format Information: linking reference library : /home/projects/courses/fall_10/ee382m-16947/Artisan/sc/apollo/tsmc18. (PSYN-878) Linking design 'or1200_alu' Using the following designs and libraries: -------------------------------------------------------------------------- or1200_alu or1200_alu.CEL typical (library) /home/projects/courses/fall_10/ee382m-16947/Artisan/synopsys/typical.db Information: The design has horizontal rows, and Y-symmetry has been used for sites. (MWDC-217) Floorplan loading succeeded. Load global CTS reference options from NID to stack Info: Writing NID in 3.0 format Info: Writing NID in 3.0 format Information: Saved design named or1200_alu. (UIG-5) about to verify_lvs Create error cell or1200_alu_lvs.err ... -- LVS START : -- Total area error in layer 0 is 0. Elapsed = 0:00:00, CPU = 0:00:00 Total area error in layer 1 is 0. Elapsed = 0:00:00, CPU = 0:00:00 Total area error in layer 2 is 0. Elapsed = 0:00:00, CPU = 0:00:00 Total area error in layer 3 is 0. Elapsed = 0:00:00, CPU = 0:00:00 Total area error in layer 4 is 0. Elapsed = 0:00:00, CPU = 0:00:00 Total area error in layer 5 is 0. Elapsed = 0:00:00, CPU = 0:00:00 Total area error in layer 6 is 0. Elapsed = 0:00:00, CPU = 0:00:00 Total area error in layer 7 is 0. Elapsed = 0:00:00, CPU = 0:00:00 Total area error in layer 8 is 0. Elapsed = 0:00:00, CPU = 0:00:00 Total area error in layer 9 is 0. Elapsed = 0:00:00, CPU = 0:00:00 Total area error in layer 10 is 0. Elapsed = 0:00:00, CPU = 0:00:00 Total area error in layer 11 is 0. Elapsed = 0:00:00, CPU = 0:00:00 Total area error in layer 12 is 0. Elapsed = 0:00:00, CPU = 0:00:00 Total area error in layer 13 is 0. Elapsed = 0:00:00, CPU = 0:00:00 Total area error in layer 14 is 0. Elapsed = 0:00:00, CPU = 0:00:00 Total area error in layer 15 is 0. Elapsed = 0:00:00, CPU = 0:00:00 ** Total Floating Nets are 0. ERROR : There are 2 nets short together. NULL (0). VSS (88078). ERROR : There are 2 nets short together. NULL (0). VDD (88077). ** Total SHORT Nets are 2. ** Total OPEN Nets are 0. ** Total Electrical Equivalent Error are 0. ** Total Must Joint Error are 0. -- LVS END : -- Elapsed = 0:00:00, CPU = 0:00:00 Update error cell ... about to verify_drc WARNING: Please make sure consistency between disk database and routed database. Because verify_drc process directly on disk database. WARNING: Advance DRC runs density check without the option "Read Cell View", this tends to produce unnecessary false errors. Create error cell or1200_alu_adrc.err ... Start to run Hercules ... .............................................................................. .............................................................................. .............................................................................. .............................................................................. .............................................................................. .............................................................................. .............................................................................. .............................................................................. .............................................................................. .............................................................................. .............................................................................. .............................................................................. .............................................................................. .............................................................................. .............................................................................. .............................................................................. .............................................................................. Hercules is done! Overall ev_engine time = 0:00:05 User=4.11 Sys=0.32 Mem=42.894 ------------------------------------------------------------------------------- Rule: Met1 Spacing : minimum spacing = 0.23 um 196 errors Rule: Met2 Spacing : minimum spacing = 0.28 um 1 error Rule: Met3 Spacing : minimum spacing = 0.28 um 1 error ------------------------------------------------------------------------------- Advanced DRC is finished. about to write reports Information: Not in mixed mode. All nets either post routed or virtual routed. closing MW lib... Removing physical design 'or1200_alu' current dir is /misc/scratch/mark/ICC/cpu/blocks/or1200_alu changing dir back to /misc/scratch/mark/ICC icc_shell> open_mw_lib /misc/scratch/mark/ICC/cpu/blocks/or1200_alu/or1200_alu.mw {or1200_alu.mw} icc_shell> open_mw_cel or1200_alu Information: Opened "or1200_alu.CEL;1" from "/scratch/mark/ICC/cpu/blocks/or1200_alu/or1200_alu.mw" library. (MWUI-068) icc_shell> quit Updating preference file: /home/ecelrc/faculty/mark/.synopsys_icc_prefs.tcl Thank you...