EE 382M VLSI-II Spring 2016
Class Project Assignment
Due: May 8
Overview of the
assignment
This project
assignment will be given out during first week of class to provide plenty of
time to complete it. The class will be assigned to teams to do the various
components of the design. The intent of the project is to do a top-down design
of an embedded SOC. The ARM M0 processor will be used as the processor core for
this project. We will be designing the ARM core with peripherals using the
Synopsys 32/28 nm open library.
The Homework assignments are intended to give the student
familiarity with the technology.
The project
activities will include:
Doing a detailed floorplan of the cluster level components.
Doing a detailed top-level floorplan using the cluster abstracts.
Determining the critical timing paths and setting the component constraints at the top level and the component level. If the critical path exceeds the timing budget, the logic will have to be re-designed or the micro-architecture will have to be re-pipelined. Timing will be negotiated among all clusters and the top-level integration team.
Doing a detailed power estimation determining the power grid requirements.
Determining the clocking
requirements and designing the clock distribution and regeneration components.
Determining the
standard cell and custom library elements needed to completely do the design
with APR tools.