*****************************************
*inverter
****************************************

.macro inv IN OUT Wp=22n Lp=22n Wn=22n  Ln=22n

M1 OUT IN vdd vdd pmos L=Lp W=Wp
M2 OUT IN 0 0 nmos L=Ln W=Wn

.eom

*****************************************
* CMOS transmission gate
*****************************************

.macro tgate IN OUT C Cb Wp=0.14u Wn=0.14u

M1 IN Cb OUT vdd pmos L=22n W=Wp
M2 IN C OUT 0 nmos L=22n W=Wn

.eom

*****************************************
* NMOS load
*****************************************

.macro load out Wn=0.22u

M2 0 out 0 0 nmos W=Wn L=22n m=1

.eom

*****************************************
*feedback
****************************************

.macro fdbk pmos0_g pmos1_g nmos0_g nmos1_g OUT Wp=22n Wn=22n

M1 n0 pmos0_g vdd vdd pmos L=22n W=Wp
M2 OUT pmos1_g n0 vdd pmos L=22n W=Wp
M3 OUT nmos0_g n1 0 nmos L=22n W=Wn
M4 n1 nmos1_g 0 0 nmos L=22n W=Wn

.eom


$****************************************************************************
$ Block: dff_c
$****************************************************************************
.macro dff_c22nm din clk out
X1 din net1 inv Wp=0.7*280n Wn=0.7*210n
X2 net1 m_ic clkn1 clkp0 tgate Wp=0.7*0.14u Wn=0.7*0.14u
X3 clk clkn0 inv Wp=0.7*100n Wn=0.7*80n
X4 clkn0 clkp0 inv Wp=0.7*100n Wn=0.7*80n
X5 clkp0 clkn1 inv Wp=0.7*140n Wn=0.7*110n
X6 m_ic net3 inv Wp=0.7*280n Wn=0.7*210n
X7 net3 s_ic clk clkn0 tgate Wp=0.7*0.14u Wn=0.7*0.14u
X8 net3 clkn0 clkp1 net3 m_ic fdbk Wp=0.7*140n Wn=0.7*140n
X9 clkn0 clkp1 inv Wp=0.7*140n Wn=0.7*110n
X10 s_ic net5 inv Wp=0.7*140n Wn=0.7*110n
X11 net5 s_ic inv Wp=0.7*140n Lp=0.7*200n Wn=0.7*110n Ln=0.7*200n
X12 s_ic net6 inv Wp=0.7*0.7u Wn=0.7*0.54u
X13 net6 out inv Wp=0.7*2.1u Wn=0.7*1.6u
X14 out load Wn=0.7*9u
.eom