1.

Part a.
Speedup = 1 / ((0.95 * 0) + 0.05) = 20

Part b.
Interrupts are caused by external events and exceptions are caused by internal events.
Interrupts are not related to the exceution of the program and are hence handled mostly when convenient.
Some interrupts such as machine check and power down are critical

Part c.
The two "clean" states in the Illinois protocol distinguish between the case when no other cache has the line, and atleast one other cache has the line. In other words, the Illinois protocol captures the information whether any other cache shares a cache line or not
This eliminates the unecessary write-through (write-once) which happens when a line which is not present in any other cache is read and then written to.

Part d.
No
0 1011 001 and 0 1011 010

2.

Part a.


i. Virtual page number is 8 bits
ii. Physical frame number is 4 bits
iii. 2 bits are used to dtermine the byte within block
iv. 4 bits of virtual address are used to index into the cache
v. Virtual page number is 8 bits
vi. Number of blocks = 64/4 = 16
Size of PTE entry = 4 bits of PFN + 1 (valid) + 1 (dirty) = 6 bits
Size of tag store = 6 * 16 = 96 bits

Part b.


vi. A physical address with PFN = 0000; say 0000 abcd
vii. 00ab and 01ab
viii. Minimum associativity required is 4

3.

  Bits    Carry  |  pre_shift     ALU_op     post_shift    carry
 -----------------------------------------------------------------
  000       0    |     3          PASS           0           0
  001       0    |     0          ADD            3           0
  010       0    |     1          ADD            2           0
  011       0    |     0          SUB            2           1
  100       0    |     2          ADD            1           0
  101       0    |     0          ADD            2           0
  110       0    |     1          SUB            2           1
  111       0    |     0          SUB            3           1
  000       1    |     0          ADD            3           0
  001       1    |     1          ADD            2           0
  010       1    |     0          SUB            2           1
  011       1    |     2          ADD            1           0
  100       1    |     0          ADD            2           0
  101       1    |     1          SUB            2           1
  110       1    |     0          SUB            3           1
  111       1    |     3          PASS           0           1


Cycles required = 4

               0 1 0 1 0 1 1 1 1
               0 1 0 1 0 1 1 1 1
After Step 1:  1 1 1 1 0 1 0 1 0 0 0 1 0 0 0 0 0 0 
After Step 2:  1 1 1 0 1 0 0 0 1 1 0 0 0 0 1 0 0 0
After Step 3:  1 1 1 0 0 1 0 0 0 1 0 1 0 0 0 0 1 0
After Step 4:  0 0 0 1 1 1 0 1 1 1 1 0 1 0 0 0 0 1

4.

Case 1: Infinity
Do nothing

Case 2: Normal numbers except exponent 0000 0001
Subtract 1 from the exponent

Case 3: Normal numbers, exponent is 0000 0001
Set the exponent to 0000 0000 (subtract 1); Right shift the fraction, shifting in a 1

Case 4: Subnormal numbers (including 0) (exponent is 0000 0000)
Right shift the the fraction

5.

Part a.


MOVI Vln, 64
MOVI Vst, 1
VLD V0, A
VSHR V1, V0
VST V1, A

88 cycles

|-1-|-1-|----11----|----------63----------|
                   |-1-|----------63----------|
                       |----11----|----------63----------|

Part b.


23 cycles (11 for the load, 1 for the right shift, and 11 for the store)

Part c.


Speedup = 88/23

6.

Answer = N/k (integer divide) for postive N & k

7.

Part a.



Part b.
Changes to datapath:

• A new input (110) to the SR1 MUX
• A new input (110) to the DR MUX
• A new control signal for DR MUX to choose among 3 inputs