Date: Thu, 11 Apr 2002 12:36:50 -0500 (CDT) From: David N. Armstrong To: EE 382N Announcement Cc: David N. Armstrong Subject: RE: Matt Merten, Wen-mei's student is interviewing for a faculty position (fwd) -----Original Message----- From: Yale Patt [mailto:patt@ece.utexas.edu] The seminar is at 10:00 AM tomorrow in ENS 637. Here are the details on his talk. Short Bio: Matthew C. Merten is a doctoral student at the University of Illinois at Urbana-Champaign, where he received his B.S. in computer engineering in 1996 and M.S. in electrical engineering in 1999. His research interests are focused on microarchitecture design and on post-link-time optimization including off-line and run-time optimization. He has published in the areas of automatic profiling, hardware-based code relayout, adaptive cache management, architecture support for modulo scheduling, and worked on projects including IA-32 and IA-64 compilation and binary reoptimization, and HP-PA to IA-64 runtime translation. Abstract for Talk: Runtime Optimization ARchitecture (ROAR) is a new architectural model that enables dynamic adaptation of executing programs to variations in important performance characteristics such as branch directions and instruction execution weights. During standard execution, the hardware behaves like an EPIC or VLIW processor that executes code according to a schedule which was explicitly arranged using profile information. An additional hardware component is employed to identify important execution paths where opportunities exist for adapting code to the current execution conditions. When such opportunities arise, a code transformation mechanism is triggered to improve code efficiency, parallelism, and schedule. This results in a new, explicitly arranged schedule for the processor to execute until further transformations become desirable. By limiting code transformations to occasional invocations, the ROAR model can potentially result in more energy efficiency and less hardware complexity in the main execution engine compared to out-of-order execution models. The ROAR model enhances the ability of EPIC and VLIW processors to deal with variations in dynamic execution conditions. By performing the code transformations at runtime, we demonstrate that ROAR processors can realize significant performance improvements over EPIC processors which execute aggressively optimized code. Thus, ROAR is a promising model for eliminating the continuous rescheduling performed in current out-of-order processors.