Department of Electrical and Computer Engineering The University of Texas at Austin ECE 382N, Spring 2002 Y. N. Patt, D. N. Armstrong Exam 1 Buzzwords Instruction Supply Data Supply Processor Core Instruction: Opcode, Operands Atomic Unit Principles, trade-offs, implementation Memory Hierarchy- capacity, latency, cost Levels of Hierarchy Algorithm Effective Computability Definiteness Finiteness Predication Static Schedule Run Time Behavior - Branch Results, Cache Hits/Misses, Runtime Operation Victim Cache Cache Control Instruction Caches - non-determinism Value Prediction Speculative Execution uCode ROM Semantic Gap Fixed Length Instructions Variable Length Instructions Uniform Decode Steering Bit "No lazy silicon" Science of trade-offs Computer Arch. as an art Mandatory & Speculative Branch Prediction Bread & butter design Compatibility (x86 instrs) Addressing mode Control & Data Path Memory Mapped I/O I/O Instructions Performance Equation CPI Cycle Time Adding NOPs Anecdote MIPS - scoreboard bits Balancing workload btwn cycles Critical Path Control Store Kids on Errands at Super Market Example uCode Atomic Operation (checking for Ints & Exceps) Machine in Consistent State - what to do with dest. writes String Operations - handling Ints & Excepts with reasonable Int Latency uOps/ROPs from Decoder or Entry Point Balanced Design Critical Path Design Performance Design Point Dependable Computing Design Point Cost Design Point Cycle Time vs. Parallelism Spec/MHz benchmark Fast Execute/Slow Commit DEC Scoreboard-- assume no dependency Tailored vs. General parts General Purpose Processor Special Purpose Processor Limited Purpose Processor Pipeline Design/Pipeline Stages Split Line Fetch Return Address Stack BTB Speculative Fetch Variable Length Instruction Fixed Length Instruction Huffman Encoding of Instructions x86 ISA x86 - Compatibility Interlocks Scoreboard Out of order execution - tags x86 segment registers - protection x86 - dense encoding of the istream sib byte, mod r/m byte sequential vs parallel decode x86 Flat Memory Model Virtual x86 Memory Model Fast Context Switching x86 Protected mode (memory model) Segment descriptors, descriptor tables Segmentation vs. Protection Capability based machine-- failed because... clock cycle vs. instr. cycle out of order completion exception handling managing complexity data type prefetch instructions, cache management instructions dynamic static interface time, space, cost trade-off power consumption issue data flow vs. systolic array vs control flow restricted data flow segmentation vs. paging chip real estate fast vs. correct special purpose vs. general purpose datapath design register alias table memory disambiguation problem (unknown address problem) memory order buffer re-order buffer return address stack branch prediction pipeline bubbles fetch rate multiple path exectution eliminate branches conditional registers delayed branch delay slots delayed branch with squashing static prediction predict based on profiling dynamic predictor last time predictor saturating 2bc saturating arithmetic btfn predicated execution 2-level predictor pattern history table branch history register [GPS][AS][gps] interference branch predictor warm up multi hybrid agree predictor gshare predictor