Department of Electrical and Computer Engineering The University of Texas at Austin ECE 382N, Spring 2002 Y. N. Patt, D. N. Armstrong Problem Set 1a FAQ Q: For our ALU design can we use NAND gates with multiple inputs (3 or more) or a max of 2 inputs per gate? A: Please restrict yourself to 2-input NAND gates (or NOR gates if you prefer) for this hwk and build the 3-input NAND gates from 2-input NANDs. This requirement is meant to get you to started using a hierarchical design right away. Q: Should we assume an initial carry-in to the adder? A: You needn't provide an initial carry-in for this adder, but you should feel free to go beyond the requirements, if you like. It could proove useful when you use this adder later on in your project. Q: Would a simple series of 16 full adders suffice for the + part of the ALU? A: If it works, it will suffice. Q: I have several ideas for making the adder faster but most of them at least double the number of gates. Should we aim for the simplest and clearest solution or the fastest solution? A: This is a design choice for you to make. Be sure to discuss the design choices and trade-offs you make in your documentation for the homework. Q: Do I need to detect overflow due to addition? A: Not required for this assignment but see previous answers regarding going above and beyond. Q: How do I show a bit-slice of the adder, in a carry-lookahead adder case or any other case, where the design is considering more than one bit of each input, at a time ? A: You're right, a bit slice doesn't necessarily make sense as your design becomes more complex. Do show the lowest or smallest section/slice that does make sense and show how you combine these together to form your solution. Q: Can we use both NAND and NOR in our design, or does it have to be all one or all the other? A: Nope, one or the other but not both. Q: Where do we have to turn in the first homework? A: I'll bring a box where you can submit the hwk just before class on Tuesday.