Department of Electrical and Computer Engineering
		  The University of Texas at Austin

			ECE 382N, Spring 2002

Y. N. Patt, D. N. Armstrong
Problem Set 1b FAQ

Q: For HW 1b,  can I use 3-input  and 4-input NAND instead of building
them from  2-input  NAND? This  will affect   the critical path  delay
calculation. 

A: Please use only 2-input NANDs,  the same requirement as in Homework
1a, and the same interest in having you do a hierarchical design. 


Q: I have  a question about  the first problem  in the  homework: What
should the select  lines of MUXa and  MUXb be connected to? Also, does
the MUXa select between the Q output of ALUout and a? 

A: The select lines  for MUXa and MUXb  must be controlled in your TOP
level  module in order to verify  the functionality of  your ALU. Yes,
muxa selects between ALUout and a new input a. 


Q: Am I supposed to figure out the minimum  cycle time that will cause
a problem  in my circuit,  using VirSim?  OR do  I arrive at  it using
cycle time >= (t_logic + t_setup + t_clktoq ) 

A: You  should do both and  verify  that you  get the same  result for
each. VCS will complain about  timing violations when you're compiling
the code, not necessarily on the waveform. 


Q: Can I change my design from Homework 1a or am I required to use the
same design?

A: You are  allowed to change the design and  encouraged to improve it
if possible.


Q: Do we need to draw the schematics of detail design of the muxes and
reigsters (we'll  use dff$ library part)  and the ALU  (we already did
for ALU in HW 1a)?

A: Please  do turn in copies  of your ALU such  that the documentation
for this  assignment stands on  its own. If  you made no  changes from
last time, a photocopy will be fine.


Q: My problem is the ALUout feeds  into muxA & muxB, which means I can
only  add two  identical  numbers together,  and  not the  alternating
pattern  [that  demonstrates the  critical  path].  I  cannot get  the
longest delay because of this situation. Am I doing something wrong?

A: MUXa  and MUXb are controlled  by different select  signals so send
the output  of ALUout through  one of the  mux's and send  a different
"new" input through the other mux.

Q: I  am trying to do  homework 1B and I  have a question  about how I
would  connect an  input directly  to  an output  in a  module. I  was
thinking that I  could use assign = , but it  says that is behavioral,
and we are only allowed to use structural. Thanks for any help you can
give me.

A:  You're ok  using  the =  sign to  connect  two wires  in the  PASS
function. As  long as there are  no +'s, &'s, etc.  Also, reg's should
only be in your TOP.v and used for exercising the alu structure.


Q: I have  a question regarding the  last part of the homework  : As I
reduce the  cycle time, I get a  point where I get  a timing violation
during  compilation. However,  this doesn't  show up  as  an incorrect
output on the  waveforms.  Do I need to  keep trying different vectors
till I get an  incorrect output, or do I need to  reduce my cycle time
further still ?

A: No, a compilation error is  your indication that the cycle time has
been reduced too  far. You won't necessarily see  incorrect results on
the waveform, but instead when you run simv.


Q:  i just  want to  make sure  that we  do not  have to  turn  in the
program, only the print-outs, right?

A: Correct, no need to turn  in code. You should include enough signal
diagrams  to answer the  questions at  the end  of the  assignment and
prove that your design works.