Department of Electrical and Computer Engineering
		  The University of Texas at Austin

			ECE 382N, Spring 2002

Y. N. Patt, D. N. Armstrong
Homework 2 FAQ


Q: Is it ok to design our own  ALU or is it compulsory to use the four
bit slice. Will we be using this ALU for our final project ?

A: The four bit slice is there  if you need it.  You are not compelled
to use  it over a  design of your  own. You will  need an ALU  in your
final project however  it needn't be the ALU  from homework 1[ab] (but
note the data size change from 16 to 32 bits).


Q: For homework  2, are we supposed to implement  our design such that
it is 100% compliant with ia32? I looked at the ADD instruction in the
Vol2 ia32  manual and there  are 14 modes  altogether.  Do we  need to
implement all of them? If we do, i assume we will need to have all the
registers in place just like intel does.

A:  You  need to  implement  the  instructions  that use  32-bit  data
values. You do need to use the intel style registers, however to start
with, you only need to  implement the 32-bit versions of the registers
(EAX -  ESP). Your design should  be x86/ia32 compliant.   If you have
specific questions on this point, though, you should ask me.


Q:  For the  Register Transfer  Notation, do  I need  to  consider the
effects on EFLAGS register?

A: Yes,  please show when  the EFLAGS are  being set in  your register
transfer notation. To do so, you might just write after the operation,
set <some specific EFLAG>; or  some other notation that makes it clear
when they're being set.


Q: Here are a couple clarifications  I made in response to a student's
question about register transfer notation:

A: 
   1.  Please  specify the segment  register you  are using  to access
memory  something like this:  Mem[disp32 +  DS <<  4] or  whatever you
think is clear.
// NOTE:  the shift amount  has since been  changed to 20 bits,  not 4
bits as shown above.
   2. Note that you can access memory with disp32 as well as the other
addressing modes in table 2-2. You'll  need to show the other modes in
your rtl as well.
   3. Please specify which of the EFLAGS are set by the instructions.


Q: JMP m16:32  - how is the 4byte offset and  the 2bit selector placed
in memory?   aren't the  contents of  memory 4 bytes?   if so,  are we
really accessing two memory spots?   what's the ordering of the offset
and selector in memory.  this instruction confuses me.

A: This is a far jump. We'll  go over it in lecture or discussion. You
do not need to worry about this case for homework 2.


Q:  do  we  have  to  do  the  move to  and  move  from  seg  register
instructions?  MOV r/m16,Sreg, MOV Sreg,r/m16

A: Don't worry about these for homework 2.


Q: I  couldn't find in  the Intel  manual on how  to get the  size (in
byte)  of the  instruction to  be fetched.   This will  be  needed for
incrementing the  EIP to prepare  for the next instruction,  since the
instruction length  for IA32 is a  variable. Could you  help with this
question?

A: x86 instructions are variable length instructions so there is not a
place in the manual where the length of instructions is specified. You
must figure this value out on a per instruction basis. The length is a
factor of a number  of things such as the presence of  a mod r/m byte,
displacement and immediate as well as a number of other things.


Q: How much do we increment  the EIP to point to the next instruction?
Do we need  to implement a counter in the  instruction decode logic to
count the  number of  bytes of the  current instruction? Then  it will
take an extra cycle.

A: You will  need to implement a mechanism  to handle incrementing the
EIP by the  appropriate amount. However, this mechanism  does not need
to be controlled  for homework 2. Therefore you do not  need to do the
extensive decoding you  describe, for homework 2 but  you will need to
do it for homework 3 and the project.


Q: Well, I'm  trying to put in  a few registers for the  EIP, MAR, MDR
etc. Are we supposed to construct  those with $dff's or can we use the
'reg [32:0] SOME_REG' notation in Verilog?

A: The reg[31:0] construct is  considered behavioral and should not be
used  in your design.  You should  use the  dff's or  other structural
constructs you  find in the libraries.  Note however that  you can use
the  reg construct in  your TOP.v  module for  the purpose  of driving
signals to test your structural design.


Q: After we do  the 4-bit shift of the segment register  and add it to
and address, do we need to worry about translating it to the PA?

A: No,  for this assignment you  don't need to worry  about virtual to
physical translation.
// NOTE:  the shift amount  has since been  changed to 20 bits,  not 4
bits as shown above.


Q: What is the class directory to put the Verilog codes for HW#2 in?

A: Make a directory in your  ece home directory.  Your quota should be
increased to accomodate these projects.


Q:  I  have a  question  regarding how  we  are  to support  segmented
addressing.   Are we  expected  to support  operations to/from  memory
locations outside the data segment?

A: In  order to  change the default  segment in  x86, one would  add a
segment  override  prefix to  the  instruction.  Because  you are  not
required to implement  prefixing in this assignment, you  only need to
access   data/code   from  their   default   segments   (DS  and   CS,
respectively).


Q: When we shift the segment register by four, we end up with a 16-bit
quantity and  the low 4 bits  being zeros. We  then add it to  the EIP
(bit0 aligned  to bit0, bit1 aligned  to bit1 etc..) and  get a 32-bit
quantity. Are my assumptions correct?

A: No, shift the seg reg by  4 to obtain a 20-bit value which you then
add to the 32-bit EIP.
// NOTE:  the shift amount  has since been  changed to 20 bits,  not 4
bits as shown above.


Q: Should I assume: use DS for ADD, XOR, MOV, INC, and use CS for JMP?

A: Yes, use  CS for the JMP instruction. This  makes sense, right? The
CS register points to code and  JMP instruction loads a new value into
the EIP, the pointer to code.
// It was pointed  out to me that this answer is  unclear. In the case
where a JMP instruction uses a memory operand in order to form the new
EIP  value, you  will  use the  DS  segment to  find  that operand  in
memory. In the above answer, I meant that the CS register is used when
fetching instructions from  memory, not the data used  to form the new
fetch address. You will not be  counted off in your homework 2 if your
RTL uses the CS segment incorrectly in JMP instructions.


Q: Does  the EIP  contain the  absolute 32-bit address  of code  to be
fetched, or does it contain  an offset address within the current code
segment? When I want to fetch an instruction, do I fetch it from [EIP]
or from  [EIP + CS  << n], where  n is the number  of bits we  shift a
segment register?

A: The EIP  register contains an offset into the  segment.  Use the CS
register as shown.


Q: After  today's class, what  is the state  of the addressing  in our
project?  Are  those of us  who already completed our  design shifting
the segment  register 4 bits and  adding it to the  offset supposed to
resdesign our data path and state machine?

A: I'm afriad it's going to  require a revision. Hopefully it's just a
small change to the datapath, shift by 20 instead of by 4, and not the
state machine.


Q: I don't really get how these instructions are decoded.

AA. 01 /r      Add r/m32,r32
BB. 03 /r      Add r32,r/m32

If I want to do Add r32,r32, but they are two different registers. How
do I  put it in the  ModR/M byte? Where does  the destination register
get decoded in the ModR/M byte? Is it in the Reg/Opcode bits?

A: The  destination register  is always the  first source  operand. In
instruction  AA., the  destiation is  r/m32; in  instruction  BB., the
destination is r32.

The /r  in the opcode indicates  that the Reg/Opcode field  of the Mod
R/M byte will be used to  indicate a register corresponding to the r32
shown in the instruction. Now, say you want to add two registers, then
you will set the Mod field of the Mod R/M byte to binary 11 (according
to Table  2-2 in Vol. 2)  and therefore the  R/M field of the  Mod R/M
byte will be used to specify the other register you want to use.


Q: Let's  use instruction AA to do  Add m32, r32: In  the ModR/M byte,
Mod & R/M  bits will specify the memory  operations and the Reg/Opcode
will specify which register, right?

A: Correct.


Q: Is it also the case if  we use instruction B to do Add r32,m32? The
Mod  & R/M  bit specifies  the  memory operations  and the  Reg/Opcode
specifies which register.

A:  Correct.   Question  for   you:  when  the  machine  decodes  this
instruction, how does it know  to store the results of the instruction
in the register specified  by in the Reg field or in  the R/M field of
the Mod R/M byte?


Q:  For the  Jmp instruction,  let's say  E9 cd:  JMP rel32.  For this
instruction, Is it  just E9 and 32 bit displacement? And  to do it, is
it just add the displacement to the EIP?

A:  The instruction  consists  of  the opcode  and  a 32-bit  relative
offset. The description on the  manual page for this under the heading
of  'Near and Short  Jumps' should  clarify for  you which  values are
relative offsets and which are absolute offsets.


Q: I have a  question: As for the datapath, do we  use two memory (one
for instruction and  the other for data) or  one memory (contains both
data and inst)?   A little research I did  about datapath suggest that
pipelined datapath has two memory. Is this correct? THanks.

A: Right, for a pipelined design, you'll want both a data memory (data
cache)   and   instruction  memory   (instruction   cache).  For   the
non-pipelined approach you would probably use one central memory as in
the LC-2 datapath. Question for you:  why do you want the split memory
for instructions and data in the pipelined design?


Q: To find out  the next instruction to be fetched, I  have to add EIP
to CS<<4, right?

A: Shift by 20 now to approximate the real address mode.


Q: But  since the EIP has  only 32 bits,  I can't store this  value in
it. That is, in  EIP I always have a value relative  to CS. So have to
do this computation every time I fetch an instruction?

A: You must fetch  and instruction with the sum of the  EIP and the CS
<<  20.   Probably what  you  will  do is,  every  time  you fetch  an
instruction, you will add the EIP to the CS register.


Q: If this  is right, in the  JMP instruction I don't have  to use CS,
right?

A: The jump instruction changes either the EIP or both the EIP and the
CS register (near  and far jumps). For this  assignment, you only need
to implement the near jumps.


Q:  But adding  EIP to  CS<<20 every  time doesn't  sound like  a good
ideia, because the time to fetch  an instruction would be the the time
for the add plus the time for the cache access, right?

A: You're right, that is a lot  to fit in a cycle. And the task before
you is to  implement this or implement something  faster that achieves
the  same  functionality.  Remember  that  the  CS  register  and  EIP
registers can be changed independently  of one another, via near jumps
and the move into segment register instruction.


Q: In case we need to use  reg files with more read ports than given -
should we duplicate the reg file or should we change the design to fit
2 ports!

A: You  could keep  multiple copies  or your could  make your  own reg
files. Have you thought about how a read port works? I can't emphasize
enough that  you should know how to  build this and in  fact, the read
port is not difficult to do.


Q: For  the INC  r32 instruction,  the opcode says  '40+ rd'.   So for
example, to perform the following: EBX = EBX + 1, it would only be a 1
byte instruction with the one byte being 0x43? Thanks.

A: Yup, that's right.


Q:  I  had  a question  about  Homework  2.   Does  the RTL  for  each
instruction need to show how the  EIP is incremented (by the length of
the  instruction) ? Since  this happens  in decode,  I didn't  think I
needed to  show that in the RTL  for each instruction but  I wanted to
check with you.

A: Nope, the RTL shows the function of each instruction, not the cycle
by cycle action. The cycle by cycle action is to be shown in the state
machine.


Q: What  subset of the 256 r32  and r/m32 combinations of  the XOR and
ADD instructions do you want us to list in RTN?
 
Is the following style of output satisfactory?

Instruction: ADD r/m32,imm32
Opcode: 81 07 id
RTN: Mem[EDI + DS<<20] <-- Mem[EDI + DS<<20] + id
Flags: AccordingToResult(OF, SF, ZF, AF, CF, PF)

Instruction: ADD r/m32,imm32
Opcode: 81 40 disp8 id
RTN: Mem[EAX + disp8 + DS<<20] <-- Mem[EAX + disp8 + DS<<20] + id
Flags: AccordingToResult(OF, SF, ZF, AF, CF, PF)

A: You're  on the right track.  Please don't tie your  notation to any
particular  register.   Instead  use  GPR  to   mean  general  purpose
register.  For the r/m  byte I  want to  see the  different addressing
modes shown in Table  2-2 in Vol. 2 (except for the  SIB byte), two of
which you show below.


Q:  had a  quck question,  when implementing  the overflow  flag, does
adding two  positive numbers and forming a  negetive result correspond
to an overflow.

A: You tell  me...  what're the arguments for and  against this as the
test  for overflow?   Does this  describe all  possible  occurances of
overflow?


Q: Also  can we  just represent  the decoder as  a blackbox,  with the
opcode going in  and the output coming out. So  how many cycles should
we assume for  the operation? If not  how much detail do u  want me to
give ?

A: You'll have to make  reasonable assumptions about this for homework
2.  Ideally, with  the extra  time, you've started  on homework  3 and
have some ideas about what's reasonable to do here.