Department of Electrical and Computer Engineering The University of Texas at Austin ECE 382N, Spring 2002 Y. N. Patt, D. N. Armstrong Homework 4 FAQ Q: Is HW4 independent of HW3? I mean in HW4, do we have to use the expanded data path in HW3, or can we use the simpler data path in HW2 (no SIB, segment override)? A: No, please continue building upon previous work. You are allowed to throw out ideas and change things around in your datapath, but you should not take the simpler datapath for homework 4 such that the control, calculations and simulations are easier to do. Q: When we design the control unit in HW4, do we need to implment the gate-level ROM or PLA, which is used to implement the microcode or finite-state-machine, in structural Verilog? It's pretty tedious. A: Use the ROM device in the libraries to make this less tedious. Q: I had a question regarding the register file provided in the library. It is behaviourally modelled. If I wanted to add a read port to it, can I add to the behavioural library model, and if so, do I make the delays the same as the existing one ? A: No, please don't write any behavioral code for this project. In order to adjust the register file, you'll need to either design one from scratch or augment the library part in a higher level module with structural parts. The library parts are your primitives and as such should not be changed by you. Q: Can I work with my group on homeworks 3 and 4? A: Homeworks 3 and 4 are still to be completed individually. I do recommend that you begin discussing the architecture of your processor with your group. However the work you turn in for homework 4 must be your own work. Please ask me if you want further clarification. Q: Homework 3 asks us to augment our datapath to support several new instructions, SIB byte mode addressing, and operations on byte-sized data. Do we need to add support to operate on byte-sized data into the HW2 instructions? e.g. does HW3 require us to support ADD r/m8, imm8? I assume that we need to add support for SIB byte mode addressing to all instructions (including the HW2 instructions). A: Yes, you'll need the ADD r/m8, imm8 and equivalents for other homework 2 instructions. And you'll also need SIB support for homework 2 instructions. Q: Today I couldn't run VCS on tick.ece.utexas.edu. It seems the VCS license has problems. The error msg is as below: Feature VCSCompiler_Net or VCSCompiler_Node does not exist in the license file. Or licensed number of users already reached for VCSCompiler_Net or VCSCompiler_Node. A: Use the sunfire machines instead of tick for vcs. Q: Will we be responsible for designing our own cache memories from library parts (e.g. from SRAM parts), or will we be provided with a library part called "cache"? A: You'll be responsible for designing your own caches using SRAM's and gates (and whatever other library parts you need). Q: To plan future design decisions, I am curious to know what the line size and latency of the Icache and Dcache will be. A: This will be per your design. Q: Is it possible to postpone the Hw4 deadline by a week? A: I'm afraid it's unlikely because we must get moving on the group project. Q: Must our design handle self-modifiying code (IP reaches stored data)? A: Nope. Q: Just wanted to confirm wether we can share PERL scripts. I have written a few perl scripts which will be of help (especially if you plan to hardwire the control). I have attached the two scripts , please let me know if we are allowed to share these perl scripts with our group members. A: Thank you for checking with me beforehand. Sharing scripts within your group will be fine after homework 4 is turned in. Homework 4 is to be individual work and so I'd prefer you not share scripts at this point as everyone needs to go through the exercise of hooking up their own control for at least one instruction once. Q: I understand that we are not allowed to add read ports to the library register file since we are not allowed to write behavioral verilog. So if I want more than a two read port register file, is it an acceptable solution to replicate the register file library part? I.e. if we maintain consistency between 2 register files than that would give me four read ports. Thanks. A: You can do this however, there are some issues. Insofar as this class is meant to teach you what's going on at the structural verilog level, you must understand how you would add more read ports to a register file. If this solution solves a time constraint problem then it's ok; if on the other hand, you chose this solution because you're not sure how to add another read port to a reg file, then it's not ok. Please be sure to discuss the trade-off you're making, time to market/additional hardware/complexity in your write-up and at the review. Q: If we are using hard-wired control, we need to specify the finite state machine. My question is, do we have to show the state diagram for all the instructions, or only for that instruction which we emulate? [clarification: this is on a non-pipelined machine.] A: I'd like to see a state machine for all the instructions. You only have to implement enough control that one instruction goes through the machine. Beyond the one instruction, you do not need to build the entire control logic in verilog, but show the control signals in your diagrams. Q: The book doesn't word the following situation very well... It says as a footnote to Table 2-3 "The [*] nomenclature means a disp32 with no base if MOD is 00, [EBP] otherwise." So is the following correct: If ModRM = 00xxx100 and the SIB byte = 00100101 then that represents DS[disp32]? A: Correct. The book follows the explaination with 3 examples for different values of the MOD field which hopefully should clear up this special case of the SIB byte. Q: Is the following correct? MOV EAX, moffs32 == EAX <-- Mem[disp32 + DS<<20] and, MOV moffs32, EAX == Mem[disp32 + DS<<20] <-- EAX A: The RTL you've written is correct, however you don't need to implement the moffs addressing mode for homework 3 or 4 (moffs would've shown up under the addressing modes heading in one of the homework assignments). Hope this helps, Q: just wanted to clarify my assumption that only mov instructions on page 3-432 are to be implemented and not the ones which operates on control registers.(page 3-437). A: The MOV instructions on page 3-432 which have the applicable addressing modes (specified on the homework assignments) are the only MOV instructions you need to implement right now. Q: The following is in response to a number of questions I've received on homework 4: A: Please be advised you do not need to implement the decode and control logic for all instructions for this assignment. Here's what you need to do: * Implement decode and control for one instruction. * Demonstrate by way of verilog simulation that the datapath and control work for the one instruction. * Implement datapath for all instructions. The design should be shown on paper and implemented in Verilog such that it is able to be compiled. This datapath should show the control signals necessary to control the blocks in your datapath, however you do not need to be able to generate every single control signal in your datapath for this homework. * The homework assignments build upon one another. For homework 4 you are responsible for every instruction, addressing mode and data type in homeworks 2 and 3, eg, the SIB byte applies to instructions from homework 2 as well. This is a clarification only, other details in the homework write up still apply even if I haven't mentioned them in this email. Q: Where can i run signalscan? how do i run it? A: This is left over from the Michigan days of this class. You'll use vcs -RPP to view the signals in stead of Signalscan. Q: I wanted to clear a doubt about 8 bit indirect register memory instructions Eg: 00 /r - Add r/m8,r8. In this case if r/m8 is used to access memory. To calculate the address of this memory location, do I add [EAX]+DS<<20 or Zero_extend[AL]+DS<<20. A: Use the one with EAX. You're always in 32-bit addressing mode unless you implement the address override prefix. This means the data which you're going to memory to get is 8-bits wide, however the address you use to find that data is still 32-bits wide. Q: Sorry, let me clarify my earlier question...I've figured some of it out... With r/m8, do we just zero-extend the register value for mod=00,01,10? A: No, use the 32-bit register. This register is used to calculate the address; it is not used as an operand. Q: Do we use r/m 16? And if so... With r/m16, "(same as above)" and sign-extend the register value for mod=11? A: AX - CX, SP - DI are the 16-bit registers to use when mod=11. Q: Also, with the operand-override prefix, do we use Table 2-1, or just use tables 2-2 and 2-3 and sign/zero extend as discussed above? A: Operand size doesn't apply to the address used to find the operand. Use the 32-bit addressing table, not the 16-bit addressing table.