Department of Electrical and Computer Engineering
		  The University of Texas at Austin

			ECE 382N, Spring 2002

Y. N. Patt, D. N. Armstrong
Homework 5 FAQ

Q: Does the simulator include anything  to simulate the slowing of our
circuits as they get larger? Are there any external tools we could use
to estimate how hideous a physical  implementation of our design would
be? 

A: As the complexity  of your design  increases,  the number of  gates
will increase, which  will slow you down.   The requirement that gates
with a  fan out greater than 5  must be buffered,  will slow you down,
also. Since this isn't a vlsi class but a logic  design class, this is
the extent to which we'll worry about these issues. 


Q: I think the hw5 faq is unclear regarding the fan out.  I can't find
any mention of fan out  on any of the  assignment specs.  Do we, or do
we not, have to obey a limit of max fan out of 5?  Please clarify. 

A: It is a project requirement that gates with a  fan out of 5 or more
require buffers. 


Q: I just wanted  to verify that I  understand the 1KB limit  on cache
size.  As I understand  it, the 1KB is the   maximum total of  I-Cache
plus D-Cache.  Also, the  1KB doesn't include  the storage needed  for
tags - meaning that we can actually use a little  more than 1KB of RAM
including the tags.  Do I have this right? 

A: Yes, you have this right.