The example (dumpsim output) contained a few errors and has been updated (9/23/2004)
Assembly file
.orig x3000
AND R0, R0, #0
HALT
.end
Object file
0x3000
0x5020
0xF025
Dumpsim output at the end of each cycle for the AND instruction
Current register/bus values :
-------------------------------------
Cycle Count : 1
PC : 0x3000
IR : 0x0000
STATE_NUMBER : 0x0012
BUS : 0x3000
MDR : 0x0000
MAR : 0x0000
KBSR : 0x0000
KBDR : 0x0000
DSR : 0x0000
DDR : 0x0000
CCs: N = 0 Z = 0 P = 0
Registers:
0: 0x0000
1: 0x0000
2: 0x0000
3: 0x0000
4: 0x0000
5: 0x0000
6: 0x0000
7: 0x0000
Current register/bus values :
-------------------------------------
Cycle Count : 2
PC : 0x3002
IR : 0x0000
STATE_NUMBER : 0x0021
BUS : 0x0000
MDR : 0x0000
MAR : 0x3000
KBSR : 0x0000
KBDR : 0x0000
DSR : 0x0000
DDR : 0x0000
CCs: N = 0 Z = 0 P = 0
Registers:
0: 0x0000
1: 0x0000
2: 0x0000
3: 0x0000
4: 0x0000
5: 0x0000
6: 0x0000
7: 0x0000
Current register/bus values :
-------------------------------------
Cycle Count : 3
PC : 0x3002
IR : 0x0000
STATE_NUMBER : 0x0021
BUS : 0x0000
MDR : 0x0000
MAR : 0x3000
KBSR : 0x0000
KBDR : 0x0000
DSR : 0x0000
DDR : 0x0000
CCs: N = 0 Z = 0 P = 0
Registers:
0: 0x0000
1: 0x0000
2: 0x0000
3: 0x0000
4: 0x0000
5: 0x0000
6: 0x0000
7: 0x0000
Current register/bus values :
-------------------------------------
Cycle Count : 4
PC : 0x3002
IR : 0x0000
STATE_NUMBER : 0x0021
BUS : 0x0000
MDR : 0x0000
MAR : 0x3000
KBSR : 0x0000
KBDR : 0x0000
DSR : 0x0000
DDR : 0x0000
CCs: N = 0 Z = 0 P = 0
Registers:
0: 0x0000
1: 0x0000
2: 0x0000
3: 0x0000
4: 0x0000
5: 0x0000
6: 0x0000
7: 0x0000
Current register/bus values :
-------------------------------------
Cycle Count : 5
PC : 0x3002
IR : 0x0000
STATE_NUMBER : 0x0021
BUS : 0x0000
MDR : 0x0000
MAR : 0x3000
KBSR : 0x0000
KBDR : 0x0000
DSR : 0x0000
DDR : 0x0000
CCs: N = 0 Z = 0 P = 0
Registers:
0: 0x0000
1: 0x0000
2: 0x0000
3: 0x0000
4: 0x0000
5: 0x0000
6: 0x0000
7: 0x0000
Current register/bus values :
-------------------------------------
Cycle Count : 6
PC : 0x3002
IR : 0x0000
STATE_NUMBER : 0x0021
BUS : 0x0000
MDR : 0x0000
MAR : 0x3000
KBSR : 0x0000
KBDR : 0x0000
DSR : 0x0000
DDR : 0x0000
CCs: N = 0 Z = 0 P = 0
Registers:
0: 0x0000
1: 0x0000
2: 0x0000
3: 0x0000
4: 0x0000
5: 0x0000
6: 0x0000
7: 0x0000
Current register/bus values :
-------------------------------------
Cycle Count : 7
PC : 0x3002
IR : 0x0000
STATE_NUMBER : 0x0023
BUS : 0x5020
MDR : 0x5020
MAR : 0x3000
KBSR : 0x0000
KBDR : 0x0000
DSR : 0x0000
DDR : 0x0000
CCs: N = 0 Z = 0 P = 0
Registers:
0: 0x0000
1: 0x0000
2: 0x0000
3: 0x0000
4: 0x0000
5: 0x0000
6: 0x0000
7: 0x0000
Current register/bus values :
-------------------------------------
Cycle Count : 8
PC : 0x3002
IR : 0x5020
STATE_NUMBER : 0x0020
BUS : 0x0000
MDR : 0x5020
MAR : 0x3000
KBSR : 0x0000
KBDR : 0x0000
DSR : 0x0000
DDR : 0x0000
CCs: N = 0 Z = 0 P = 0
Registers:
0: 0x0000
1: 0x0000
2: 0x0000
3: 0x0000
4: 0x0000
5: 0x0000
6: 0x0000
7: 0x0000
Current register/bus values :
-------------------------------------
Cycle Count : 9
PC : 0x3002
IR : 0x5020
STATE_NUMBER : 0x0005
BUS : 0x0000
MDR : 0x5020
MAR : 0x3000
KBSR : 0x0000
KBDR : 0x0000
DSR : 0x0000
DDR : 0x0000
CCs: N = 0 Z = 0 P = 0
Registers:
0: 0x0000
1: 0x0000
2: 0x0000
3: 0x0000
4: 0x0000
5: 0x0000
6: 0x0000
7: 0x0000
Current register/bus values :
-------------------------------------
Cycle Count : 10
PC : 0x3002
IR : 0x5020
STATE_NUMBER : 0x0012
BUS : 0x3002
MDR : 0x5020
MAR : 0x3000
KBSR : 0x0000
KBDR : 0x0000
DSR : 0x0000
DDR : 0x0000
CCs: N = 0 Z = 1 P = 0
Registers:
0: 0x0000
1: 0x0000
2: 0x0000
3: 0x0000
4: 0x0000
5: 0x0000
6: 0x0000
7: 0x0000
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