Saturday, September 26, 2009 8:18 PM,
A student writes: Dr. Patt, Can you explain to me how condition codes work again with an example? I'm not quite sure if I have to have a previous stored value that it looks at to determine NZP or if it's just the previous result. Thanks, <<name withheld to protect the student doesn't yet understand NZP>> I had thought that the book was pretty clear on how condition codes work. However, since some of you may not have understood it in the book, let me try again, ...and more slowly. You know that in the execution of an instruction, the computer goes through a sequence of phases, the totality of which is called the instruction cycle. Not all phases are needed for all instructions: that depends on the opcode. All instructions go through the first two phases: Fetch and Decode. Do you understand why? If the instruction is a load (LD, LDI, or LDR) or an operate (ADD, AND, or NOT), the last thing the computer does in processing the instruction is write a value into a register. If it is a load, it is the value that was read from memory. If it is an operate, it is the result of the operation performed in the ALU (the add, and, or not). At the same time the computer writes the value into the register, the computer also stores information as to whether that value is negative, zero, or positive. The computer does that by writing a 1 into the one-bit register corresponding to whether the value is negative, zero, or positive, and writing 0 into the other two one-bit registers. For example, if the value is -23,067, the computer sets N to 1, Z to 0, P to 0. For example, if the value is 0, the computer sets N to 0, Z to 1, P to 0. For example, if the value is +5, the computer sets N to 0, Z to 0, P to 1. Every time the computer processes LD, LDR, LDI, ADD, AND, or NOT, these three one-bit registers get set as stated above, clobbering the values that were in there at the time. Most people call these one-bit registers "condition codes" because they contain the condition of the last value written into a register. Intel calls them FLAGS, deriving the term from the semaphore flags that you might see on a ship. HOW DO THEY WORK? Suppose you want to do one thing if the values in R1 and R2 are equal, and want to do something else if those two values are not equal. If they are equal, suppose you want the computer to add 1 to R3, but if they are not equal, you want to add 2 to R3. In both cases you want to continue on to the next task after adding 1 or adding 2 as appropriate. The code would look like this (spacing provided between the 0s and 1s to improve readability): 1 1001 010 010 111111 ; Complement the value in R2 2 0001 010 010 1 00001 ; Add 1 to R2, now R2 contains minus original value 3 0001 100 010 0 00 001 ; Add current R2 to R1, put result in R4 4 0000 010 000000010 ; If R1,R2 originally equal, branch to the add 1 5 0001 011 011 1 00010 ; Since R1,R2 originally not equal, add 2 to R3 6 0000 111 000000001 ; Branch to the next task 7 0001 011 011 1 00001 ; Since R1,R2 originally equal, add 1 to R3 8 xxxx xxxxxxxxxxxx ; the first instruction of "the next task" Do you see why instructions 1 and 2 form the negative of the value originally in R2? Instructions 1,2,3,5, and 7 will all set the condition codes. The only one you care about is instruction 3 because the Z condition code (usually called "Z bit") is set to 1 if R1 was originally equal to R2, and the Z bit is set to 0 if R1 was originally not equal to R2. Very important: Do you understand why the Z bit is set as I just described? Since instruction 4 is a Branch, it examines the Z bit set by instruction 3. Very important: Do you see why instruction 4 only considers the Z bit? If R1 was originally equal to R2, the branch is taken and instruction 7 is executed next. If R1 was not originally equal to R2, the branch is not taken and instruction 5 gets executed next. By the way, you notice that instruction 6 is a branch, and all condition codes are tested. Do you understand why we want to test all three condition codes? Hope this helps. Good luck on the first program. Yale Patt