Saturday, November 14, 2009 5:23 PM,

A student writes:



	 Hey, Dr.Patt,
 


Hey, Mr. Student,



	 I was just reading over I/O and the KBSR/KBDR. When the address of the 
	 KBSR is load in the MAR, how does the machine know to access the KBSR?
	
	 <<name withheld to protect the student who addresses me with "Hey>>



If you look at Figures 8.2, 8.4, and 8.9, you will notice that there is a box 
labeled Address Control Logic.  One of the inputs to that box is the address 
(i.e., the contents of the MAR).  The outputs provide the control signals to 
deal with memory and to deal with each of the I/O registers.

So, the simple answer is, that box (Address Control Logic) examines the 
address and knows, based on what it is, whether the access is for memory or 
one of the I/O registers, and if an I/O register, which one.

We can talk more about this at the Review Session Monday evening, if you wish.

Good luck preparing for the 2nd exam.  I thought it was very nice of the 
football team to play their game early today, so you have the rest of the day 
to study.  I must remember to send them a thank you note.

Yale Patt