Tuesday, November 17, 2009 8:13 PM,

A student writes:



	 Hi,
	 
	 With regards to the DSR and KBSR, when are the ready bits set to zero 
	 after the respective data registers have been read/written? For 
	 example, in the input routine:
	 
	 START	LDI R1, KBSR
	 	BRzp START
	 	LDI R0, KBDR
	 	BRnzp next_task
	 KBSR .FILL xFE00
	 KBDR .FILL xFE02
	 
	 the read bit is polled over and over until a user hits a key, and the 
	 KBDR is set and the ready bit becomes 1. but, when is the ready bit 
	 unset? is seems that this should be done automatically, when the first 
	 instruction reads the value from KBDR, but the book doesn't seem to 
	 say (well, i can't find it anywhere).
	 	
	 on page 206, however, when discussing the analogous DSR, the book says 
	 writing to DDR clears DSR[15]. does this mean resetting the status 
	 registers is done automatically? is this something that the address 
	 control logic takes care of this behind our backs, because the book 
	 doesn't seem to clarify.
	 
	 Thanks,
	 <<name withheld to protect the student who missed that one in class>>



Yes, they are done "automatically."  That is, as I thought I told you in 
class, the first time the corresponding data register is accessed, the ready 
bit of the status register gets cleared.  You can think of it as beeing 
controlled by the Address Control Logic.

That is, the ready bit gets set by the Keyboard electronics when KBDR is 
loaded with the ascii code corresponding to the key that was typed.  This is a 
signal to the program that input data awaits.  When KBDR is read, the ready 
bit gets set as a consequence of the reading.  That is a signal to the program 
that input data does NOT await.  If it is not in the book, it should be.

With the DDR and DSR, the same basic model.  The ready bit is set, indicating 
that the DDR is ready for the next input.  The act of putting an ascii code 
into DDR clears the bit, signaling that the DDR is no longer ready for the 
next character.  Indeed, that is the case since the ascii code placed into the 
DDR has not been written to the screen yet.  When the act of writing it to the 
screen finishes, the ready bit is set to 1, indicating readiness to accept 
anohter ascii code.

OK?

Good luck, tomorrow.

Yale Patt