EE 306: Email Thursday, November 26, 2009 9:19 PM,

Thursday, November 26, 2009 9:19 PM,



A student writes:
	


	 Dear Dr. Patt,
	 
	 I am currently reading and analyzing chapter 10.2 and I have a few 
	 questions about interrupts.
	 
	 First, I know programs with higher PL can interrupt programs wither 
	 lower PLs, but how do we enter the PL in bit [10:8] to indicate the 
	 program's PL?



You don't enter it.  As far as your program goes, the operating system will 
assign you a priority level when it starts running your program.
In our case, we will just assume (which is a good assumption, actually) that 
your priority level is 0.  i.e., PSR[10:8] = 000.

As far as the hardware devices are concerned, they can either be hardwired at 
a specific priority level or they can be specified by the operating system.
I have seen ISAs that do it both ways.



	 I mean how does the LC-3 know that it's a PL, and not something else, 
	 like part of an address or a register?



I am not sure what you mean by this question.  Every process, whether it be an 
application program or an interrupt service routine executes with a PSR.  Bits 
[10:8] of the PSR associated with that process contains the priority level 
that the process runs at.

What the LC-3 hardware does is compare the priority of the process that is 
running with the priority of the device that wants to interrupt.  If the 
device priority is higher, it interrupts.  If the device priority is lower or 
the same as the process running, the device does not interrupt.



	 Second, I know that the keyboard can intialize an interrupt, but I 
	 can't visualize it in assembly language form. How can the LC-3 
	 differentiate between 2 different interrupting program (one higher PL 
	 than the other), if the intialization both come from the keyboard?



The LC-3 can not distinguish.  ...and does not have to.  Recall in class I 
told you that when a device wants to interrupt, it does so by transmitting 
three pieces of information:

1. A one-bit signal saying "I want service NOW"
2. A three-bit signal that is the priority level of the device.
3. An 8-bit interrupt vector (like the trap vectors you are used to)

The one-bit signal causes the LC-3 to compare PSR[10:8] with the three-bit 
priority level from the device.  If the three-bit priority level is not higher 
than PSR[10:8] of the process running, the LC-3 allows the current process to 
continue executing.  If it is higher, the LC-3 pushes the PC and PSR of the 
program that is running on the stack and sets the PC to the starting address 
of the interrupt routine.  The LC-3 gets the starting address from the 
interrupt vector table in the same way it got the starting address from the 
trap vector table.



	 Finally, what kind of code do we use to access the interrupt vector 
	 table? I read that part and am confused about the function of the 
	 vector table.



No code.  It works just like the trap vector table.  The only difference is 
the trap vector table is accessed due to a TRAP instruction.  The interrupt 
vector table is accessed due to an interrupt signal as described above.  In 
our example, that signal is generated by KBSR[15:14] = 11.  That is, the IE 
bit is 1 and someone typed a key, making KBSR[15] equal 1.

One more thing that might help.  You are well aware of the state machine that 
shows the processing that goes on every cycle, and the way the LC-3 gets from 
one state to the next.  You know that from state 32, the LC-3 goes to one of 
15 possible next states, depending on the opcode, and carries out the next 
sequence of states depending on that opcode.  The interrupt sequence is sort-
of like that of an opcode, except it does start after decode (state 32).  It 
starts at the beginning of the instruction cycle. 

Recall, from state 18, we either go to the second cycle of the FETCH phase or 
we start the cycle by cycle initiating of the interrupt as described above.  
You could, I suppose, think of the interrupt as a "non-opcode"
(I just made up this name) that processes a sequence of states if an interrupt 
of higher priority is present.  That sequence consists of pushing PC and PSR 
of the process that is executing on the stack and loading PC with the starting 
address of the interrupt service routine.  At that point, the "instruction 
cycle" of the interrupt "non-opcode" is finished, and the LC-3 is ready to 
fetch the next instruction.



	 Sincerely,
	 <<name withheld to protect the student who is ready to get back to 
	 work>>



OK?

Good luck getting done the last few tasks standing between you and the end of 
the semester.

Yale Patt