Sunday, December 06, 2009 1:24 AM,

A student writes:



	 Hello Professor Patt.
	 
	 i have questions about two topics:
	 
	 assumptions i hold true:
	 the Saved. SSP and Saved. USP are Registers which are used to store the 
	current location of the supervisor or user stack.
	 


True, except I would have said the current locations of the TOPs of the two 
stacks. 
 


	 the difference between a supervisor program and user program is that 
	 the supervisor (psr[15] is a 1)  program has more accessablity.



Also, almost true.  We have adopted the convention that psr[15]=0 means 
privilege.
 


 	the only thing that determines one program to interrupt another are 
	 the Priority Levels not psr[15]



Yes, priority determines whether one program can interrupt another.  
Recall all my analogies in class.  And, to interrupt, an event has to have 
HIGHER priority than what is currently running.  So, your grandfather can 
interrupt you, but your twin brother can not.
 


	 so my question is the following: why do we have two different stack 
	pointers?
 


To answer this, we have to understand why we have two levels of privilege.  
Answer : because we want to give some programs access to things that users are 
not allowed access to.  For example, certain regions of memory can only be 
accessed if the executing program is running in privileged mode.  Certain 
instructions can only be executed (like HALT if there was a halt instruction 
or RTI) if the program is running in privileged mode.  Basically, the core of 
the operating system (which we call the kernal) and all the interrupt routines 
and the I/O TRAP routines generally operate in privileged mode.  
Some ISAs have many levels of privilege, others have two: privileged and not 
privileged.  LC-3 has two, and therefore one bit psr[15] is all that is needed 
to differentiate them.  When there are two, we generally use the words kernal 
and user to identify the two privileged modes.  The interrupt routines are 
stored in privileged memory.  The interrupt and TRAP vector tables are stored 
in privileged memory, since we certainly would not want some malicious user to 
change the starting addresses of those routines.

So, two stacks, so that a program operating in user mode can not get access to 
the kernal (or what we have called supervisor) stack.
Recall, stacks are just contiguous regions of memory, with R6 pointing to the 
top element.  When the program is running in privileged mode,
R6 contains the same value as Saved.SSP.  When the program is running in user 
mode, R6 contains the same value as Saved.USP.



	 it seems we could get away with having only one stack



We could at the risk of allowing a malicious user to do us in.



	 and why is it that in our program we never save R6 into the Saved. USP, is 
	it because we never swithced Supervisor Privellage Program?



Aha!  An important point you are missing.  Saved.SSP and Saved.USP are 
registers in the microarchitecture, like MAR and MDR, and NOT registers in the 
ISA.  The switching happens when an interrupt is taken.  That is, when an 
interrupt occurs, the microcode initiates the interrupt by doing several 
things.  It loads Saved.USP with R6, and then loads R6 with the Saved.SSP, 
Then the PSR and PC get pushed on the privileged stack and psr[15] is set to 
0.  And finally, the PC is loaded with the starting address of the interrupt 
service routine.

All that happens in response to an interrupt interrupting the program that was 
running.  Now the interrupt service routine executes until it is done.  
The interrupt service routine is in privileged memory, which is no problem 
because on initiation, psr[15] was set to 0.  The interrupt service routine 
completes with an RTI, which can only be executed if psr[15] is 0.  The 
supervisor stack gets popped twice, the PC gets loaded, the PSR gets loaded, 
and if the new psr[15]=1, indicating that we are returning to User Mode, the 
Saved.SSP gets loaded with R6, R6 gets loaded with the contents of Saved.USP, 
and we are back where we left off running in user mode.



	 my second topic is about the KBSR:
	 assumptions made: the KBSR bit 15 is cleared only when The Data is 
	 retrieved from the KBDR. Until then, the KBDR is disabled from getting any 
	new inputs.
	 
	 Question: so from the programmers point of view, unitl the LDI 
	 instruction has taken place the the KBDR cannot take any new informatinon 
	correct?



For our purposes in our very simple machine, yes.



	 so when we are writting our interrupt program all we have to do is 
	 Load the typed key from the KBDR (not worrying about checking the KBSR) 
	 correct?
	 and once the LDI has taken place, the KBSR bit 15 will be cleared correct?
 


Correct on both counts.  We don't have to check KBSR[15] because if it were 
not 1, we would not have had an interrupt.

The first instruction that reads KBDR causes (by electronic circuits) KBSR[15] 
to be cleared.
 


	 thanking you in anticipation
	 <name withheld to protect the student who has started preparing for 
	 the final>



You are welcome.  Good luck on the final.

Yale Patt